Scatter-Gather DMA Controller

Direct Memory Access (DMA) is a technique for transferring blocks of data between system memory and peripherals without a processor (e.g., system CPU) having to be involved in each transfer. DMA not only offloads a system’s processing elements, but can transfer data at much higher rates than processor reads and writes.

Scatter-Gather DMA augments this technique by providing data transfers from one non-contiguous block of memory to another by means of a series of smaller contiguous-block transfers. The Lattice Scatter-Gather DMA Controller core implements a configurable, multi-channel, WISHBONE-compliant DMA controller with scatter-gather capability.

Features

  • Supports up to 16 physical channels
  • Up to 8 sub-channels per physical channel
  • Four priority levels using round-robin arbitration (weighted or simple)
  • WISHBONE bus widths from 8 to 128 bits
  • Simple DMA, split transfers, scatter-gather
  • Direct interface to external RAM for packet buffering
  • Autonomous and hardware-directed retry
  • Supports WISHBONE burst and classic-cycle transfers
  • Supports centralized and distributed DMA control architectures

Jump to

Block Diagram

Performance and Size

ECP5 (LFE5U)1
Core Configuration Device SLICEs LUTs Registers fMAX (MHz)
Config 3 LFE5U-85F-8BG756C 2570 4049 1637 160

1. Performance and utilization data are generated using anLFE5U-85F-8MG756C device with Lattice Diamond 3.4 software using Synopsys Synplify Pro for Lattice J-2014.09L. Performance may vary when using a different software version or targeting a different device density or speed grade within the ECP device family.

ECP5 (LFE5UM1
Core Configuration Device SLICEs LUTs Registers fMAX (MHz)
Config 4 LFE5UM-85F-8BG756C 1998 3222 1265 165

1. Performance and utilization data are generated using an LFE5UM-85F-8BG756C device with Lattice Diamond 3.4 software using Synopsys Synplify Pro for Lattice J-2014.09L. Performance may vary when using a different software version or targeting a different device density or speed grade within the ECP5 device family.

LatticeECP31
Core Configuration Device SLICEs LUTs Registers fMAX (MHz)
Config 1 LFE3-95EA-7FN672C 2670 4300 1932 145

1. Performance and utilization data are generated using an LFE3-95EA-7FN672C device with Lattice Diamond 3.4 software using Synopsys Synplify Pro for Lattice J-2014.09L. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family.

LatticeXP21
Core Configuration Device SLICEs LUTs Registers fMAX (MHz)
Config 2 LFXP2-40E-6F672C 2139 3443 1355 120

1. Performance and utilization data are generated using an LFXP2-40E-6F672C device with Lattice Diamond 1.0 software using Synopsys Synplify Pro for Lattice D-2009.12L-1. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeXP2 family.

Ordering Information

Family Part Number
ECP5 DMA-SG-E5-U/DMA-SG-E5-UT
LatticeECP3 DMA-SG-E3-U1
LatticeXP2 DMA-SG-X2-U1

IP Version: 2.5.

Evaluate: To download a full evaluation version of this IP, go to the IPexpress tool and click the IP Server button in the toolbar. All LatticeCORE IP cores and modules available for download will be visible. For more information on viewing/downloading IP please read the IP Express Quick Start Guide.

Purchase: To find out how to purchase the IP Core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Scatter-Gather Direct Memory Access Controller IP Core User's Guide
IPUG67 1.8 3/1/2015 PDF 3.8 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
IPexpress Quick Start Guide
8/5/2010 PDF 304.8 KB


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