D16550: Configurable UART with FIFO

DCD LogoThe D16550 is a soft Core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C550A. The D16550 allows serial transmission in two modes: UART mode and FIFO mode. In FIFO mode internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit directions. D16550 performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU.

The CPU can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt). D16550 includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to (2 16 -1), and producing a 16 x clock for driving the internal transmitter logic. Provisions are also included to use this 16 x clock to drive the receiver logic. The D16550 has complete MODEM control capability, and a processor-interrupt system. Interrupts can be programmed to the user's requirements, minimizing the computing required to handle the communications link.

The configuration capability allow user to enable or disable during Synthesis process the Modem Control Logic and FIFO's Control Logic, or change the FIFO size. So in applications with area limitation and where the UART works only in 16450 mode, disabling Modem Control and FIFO's allow to save about 50% of logic resources.

Features

  • Software compatible with 16450 and 16550 UARTs
  • Two modes of operation: UART mode and FIFO mode
  • Configuration capabilities
  • In the FIFO mode transmitter and receiver are each buffered with 16 byte FIFO to reduce the number of interrupts presented to the CPU
  • Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data
  • In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data
  • Independently controlled transmit, receive, line status, and data set interrupts
  • False start bit detection
  • 16 bit programmable baud generator
  • Independent receiver clock input
  • MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD)
  • Fully programmable serial-interface charac-teristics:
    • 5-, 6-, 7-, or 8-bit characters
    • Even, odd, or no-parity bit generation and detection
    • 1-, 1.5-, or 2-stop bit generation
    • Baud generation
  • Complete status reporting capabilities
  • Line break generation and detection. Internal diagnostic capabilities:
    • Loop-back controls for communications link fault isolation
    • Break, parity, overrun, framing error simulation
  • Full prioritized interrupt system controls
  • Fully synthesizable static design with no internal tri-state buffers

Applications

  • Serial Data communications applications
  • Modem interface

Jump to

Block Diagram

Performance and Size

Device1 Speed grade LUTs/PFUs Fmax
SC -7 541/232 253 MHz
ECP2 -7 529/232 177 MHz
ECP2M -7 529/232 177 MHz
XP -5 569/239 130 MHz
XP2 -7 410/227 130 MHz
ECP -5 569/239 143 MHz
EC -5 569/239 166 MHz
ispXPGA -4 415/144 78 MHz
ORCA 4 -3 410/92 72 MHz
ORCA 3 -7 385/78 47 MHz

1 FIFOs implemented in RAM's - 304 Bits

Ordering Information

This IP core is supported and sold by DCD, contact DCD at support@dcd.pl or visit their website at www.dcd.pl for more information.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
DCD: D16550: Configurable UART with FIFO
2.11 6/22/2007


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