Lattice Radiant Version History

Radiant 2.2

  • Device Support:
    • CrossLink-NX Device Family (LIFCL)
      • 17K and 40K devices bitstream enabled.
    • Certus-NX Device Family (LFD2NX):
      • 40K (-7/-8/-9) HP/LP 1.0V (COM/IND) - CABGA196
      • 40K (-7/-8/-9) HP/LP 1.0V (COM/IND) - CSFBGA121
      • 40K devices bitstream enabled
  • Tool and Other Enhancements:
    • Programmer – Supports full encryption and authentication
    • Simulation tool change – Mentor ModelSim® is the new OEM simulation tool included with Radiant software. ModelSim replaces Aldec-Active HDL™.
              NOTE: For post-routing simulation, please use a full version of ModelSim PE. The OEM version will be addressed in an upcoming software release
    • Reveal – Reveal Analyzer/Controller support for CrossLink-NX (LIFCL) and Certus-NX device families.
    • Soft Error Injection – Soft Error Injection (SEI) Editor allows you to generate single-bit errors, insert them into a bitstream, and detect them for analysis, simulating the effect of radiation damage on the device’s configuration memory./li>

Radiant Update 2.1

  • Device Support:
    • Certus™-NX Device Family (LFD2NX) offers the following 40K device:
      • 40K (-7/-8/-9) HP/LP 1.0V (COM/IND) – Bitstream Disabled
        • CABGA256
      Note: Bitstream generation is disabled for CrossLink-NX devices for this release, but bitstream for LIFCL-40K is expected to be enabled in the upcoming Service Pack (Radiant 2.1 SP1).
  • Tool and Other Enhancements:
    • Physical Designer – The Physical Designer provides a central location where a user can do all the floor-planning and be able to view the physical layout of the design.
    • FPGA Libraries -- New Primitives:
      • CRE (LFD2NX) only. License controlled.)
      • FIFO16K
    • Pin Migration - This release adds Pin Migration support, allowing user to view devices that are of the same family and package as your current device and view incompatible pins.
    • Security – The LFD2NX device supports user mode Cryptographic Engine (CRE).
    • SystemVerilog Support – as follows:
      • Lattice Synthesis Engine – The ability to read and synthesize SystemVerilog.
      • File Hierarchy View – The ability to read and produce a hierarchical file view of design.
      • Hierarchy Viewer – The ability to read and produce hierarchical view in Design Constraint Editor, Netlist Analyzer, Floorplan View.
      • Reveal – support for SystemVerilog for Reveal Controller, Reveal Analyzer, and Reveal Inserter.

Radiant Update 2.0.1

  • Device Support:
    • CrossLink-NX™ Device Family offers new 17K devices and adds new 40K packages:
      • 17K (-7/-8/-9) HP/LP 1.0V (COM/IND) – Bitstream disabled
        • CABGA256
        • CSFBGA121
        • QFN72
        • WLCSP72
      • 40K (-7/-8/-9) HP/LP 1.0V (COM/IND)
        • CSFBGA121
        • CABGA256
  • Tool and Other Enhancements/Updates:
    • IP Evaluation for CrossLink-NX 40K devices – If you don’t have licenses for the soft intellectual properties (IPs) downloaded from “IP on Server,” you can evaluate these soft IPs for approximately four hours before the device resets itself.
    • New Foundation IPs - Four new foundation IPs are added:
      • 1D Filter
      • Adder Tree
      • Barrel Shifter
      • DSP_Mult_Mult_Accumulate
    • Programmer – Programmer has enhanced support for the Security features including Flash protection (128-bit device password) and AS-256 Encryption and Lock.
    • Security Tools (Key Generation) – A new Radiant Bitstream Security Setting tool has been added that allows you to generate and verify keys that are used for bitstream obfuscation. The GUI provides user entry for Flash protection (128-bit device password) and AES-256 Encryption.
    • sysCONFIG – A new attribute, CONFIGIO_VOLTAGE_BANK0/1, has been added for sysCONFIG.
    • Updated Radiant Tutorial for CrossLink-NX – An updated Tutorial has been added using the CrossLink-NX Evaluation Board.

Radiant 2.0

  • Device Support:
    • CrossLink-NX Device Family for the following packages:
      • 40K (-7/-8/-9) HP/LP 1.0V (COM/IND) - CABGA400
      • 40K (-7/-8/-9) HP/LP 1.0V (COM/IND) - CSBGA289
      • 40K (-7/-8/-9) HP/LP 1.0V (COM/IND) - QFN72
      The Lattice Radiant Software Guide for Lattice Diamond Users has been enhanced to help users to migrate their designs to CrossLink-NX devices using the Radiant software. Users with designs on such Lattice devices as CrossLink and ECP5, designed using Lattice Diamond software, can use this guide to quickly grasp concepts of the new features of CrossLink-NX devices and designing with the Radiant software.
  • Tool and Other Enhancements:
    • Device Constraint Editor – Updates and enhancements have been added to Device Constraint Editor.
    • ECO Editor – A new Radiant software tool has been added that supports interactive Engineering Change Order (ECO) editing.
    • Floorplan View – Updates and enhancements have been added to Floorplan View. Updates include a new I/O placement feature that is used for I/O assignment such as DDR interface, DQS and clock assignments.
    • IP Catalog – Updates and enhancements have been added to Modules.
    • Power Calculator – Updates and enhancements have been added to support CrossLink-NX devices.
    • Propagation of IP Constraints – Radiant software now supports hierarchical constraints in IP applications and writes a new constraint file to propagate lower level constraints to top level under predefined constraint design rules.
    • Reveal Controller – A new Radiant software tool has been added for the CrossLink-NX family to create virtual control switches/LEDs; reading/writing to bank of registers/memory; and read/write access to control and status registers of PLL, I2C/FIFO, DPHY, CDR and PCIe hard-IPs.
    • Run Manager – A new Radiant software tool has been added that is used to run multiple synthesis and place and route passes, compare the results of multiple implementations for further analysis to get best solutions.
    • Source Templates – New CrossLink-NX templates have been added for both Verilog and VHDL in Source Template. In Source Template Editor, see:
      • Verilog > Primitive Templates > lifcl Primitive
      • VHDL > Primitive Templates > lifcl Primitive
    • Simultaneous Switching Outputs (SSO) Calculator – A new Radiant software tool has been added that estimates Simultaneous Switching Noise (SSN) affecting a victim pin according to the switching characteristics of aggressor pins.
    • Timing Constraint Editor – Updates and enhancements have been added to Timing Constraint Editor.

Radiant 1.1

  • iCE40 UltraPlus device enhancements and bug fixes
    • New HDL attribute RGB_TO_GPIO.
    • Four new iCE40 UltraPlus bitstream strategy options have been added:
      • Enable Warm Boot
      • Set All Unused IO No Pullup
      • Set NVCM Security
      • SPI Flash Low Power Mode
  • Enhanced Intellectual Property (IP) tools and flow
  • Constraints Syntax and Flow updates
    • Timing Constraints: Added Object Access Command (-of_objects) support which allows flexible and efficient object accesses. Note that this option is supported in constraint files only in Radiant software 1.1. Graphical User Interface support for this option is expected in Radiant 1.2.
    • Physical Constraints: Added -region option support in ldc_prohibit constraint. This option is also supported in ldc_set_location.
    • Timing Constraint Editor:
      • Added set_load constraint
      • Added Disable/Enable checkbox that allows you to easily disable or enable constraints.
  • Tool and Other Enhancements
    • Cross-probe timing path from timing reports. Map and PAR timing reports now have hyperlinks that allow users to view timing paths in Netlist Analyzer, Physical View, and Floorplan View.
    • Detachable Tool Windows. Detach and attach functionality has been added for all tools and views, allowing user to work on a tool outside of the Radiant software environment.
    • Lattice Synthesis Engine (LSE). LSE has significant performance improvements from Radiant software 1.0 including:
      • Improvements in embedded block RAM (EBR), finite state machine (FSM), and digital signal processor (DSP) extraction.
      • Improvements in Area implementation and run time.
    • Power Estimator. A new stand-alone Power Estimator has been added.
    • Simulation Wizard. The Simulation Wizard has been updated to support post-synthesis simulation.
    • Source Template. A new Source Template tab has been added to make it easier to access various templates without the need to have the Source Editor running. The selection of templates has been enhanced. Available templates, in both VHDL and Verilog, include:
      • Common Templates
      • PMI Templates
      • Primitive Templates
      • Attribute Templates
      • Encryption Templates
      • Timing Constraints
      • Physical Constraints
    • Ubuntu operating system. Support for Ubuntu operating system LTS 16.4 has been added

Radiant 1.0 SP1

  • Re-compile with this service pack if users uses the LVDSE IO type in their design.
  • If CCU2 primitives are indicated in the Area Report of the LSE synthesis report file, there is a chance of getting an incorrect synthesis result from carry chain optimizations. It is advised to re-compile the design using this service pack to avoid a simulation and/or hardware operation failure. This fix is applicable for LSE only.
  • Fixed several other key customer defects resolving instability relating to map, place and route in the timing engine.

Radiant 1.0

  • Standardized Timing and Physical Constraints utilizing the popular SDC format to help you easily apply constraints to your designs.
  • Unified Static Timing Analysis from Synthesis to Place & Route to accelerate design timing closure.
  • Enhanced IP Security Flow and Ecosystem to allow efficient distribution of Soft IP’s and to improve 3rd Party Soft IP security.
  • New and Simplified GUI design with option of light or dark color theme.
  • Simplified and Efficient Design Flows and Tools to improve Ease-of-Use.
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