Boost design performance and lower solution cost: Design optimizations performed by synthesis while the design is targeted to the FPGA directly impact the design’s operating performance and its cost. LSE applies a unique recipe, specifically tuned to Lattice FPGA devices.
Easy to try: Full Verilog and VHDL language support, combined with industry standard attributes and SDC constraints enables you to easily run your design through LSE and see if your results are better. It is available to use from both Diamond and iCEcube2.
Road-tested: LSE has been included with Diamond and been in active customer use since 2010. LSE was added to iCEcube2 in early 2013.
- Support for MachXO, MachXO2, MachXO3L, ECP5 and iCE device families
- Fully integrated into the Diamond and iCEcube2 design environments. Easy to switch between using Synplify Pro and LSE for the synthesis step.
- Support for industry standard Verilog and VHDL language (including mixed), along with industry standard attributes and SDC constraints. Enables the user to easily synthesize existing designs using LSE.
- GUI tool support for constraint entry (LDC Editor) and schematic netlist viewing & analysis (Netlist Analyzer) reduces the time required for design entry and analysis.
- Choice of optimization goals: Area, Balanced, Timing enables the user to highlight which design goals should be emphasized.
- See full list of features below
Why Synthesis Choice Matters
Synthesis is a critical step to convert a design from its HDL to the bits used to program the FPGA. A single synthesis tool cannot create the best results for all architectures. Differences in the order that optimizations are applied, and differences in the scope of architectures supported can both result in different results. The synthesis step has the most potential to improve the quality of results in FPGA design. Even if timing is met, further optimization in synthesis might enable targeting a lower cost, lower speed-grade FPGA which can save 15%-30% on costs.
Synthesis quality of results (QoR) is affected by the design snapshot after the HDL parsing, the tool flow, and the order in which the optimizations executed. Because of this some tools may perform better on some set of designs than other tools. Having a choice allows a designer to see design performance on different tools with different commercial options before finalizing the design.
Lattice Synthesis Engine (LSE) is a logic-synthesis tool designed specifically to produce the best possible results for Lattice’s FPGAs. It synthesizes HDL designs to netlist files constructed with Lattice specific primitives. LSE converts description of digital system to the actual high performance circuits of Lattice technology, recognizing and implementing high-level abstract structures like RAMs, ROMs, finite state machines (FSMs), arithmetic operators, and other elements.
The tool is designed to optimize a given HDL design to specific performance goals: Area, Timing or Balanced. The tool optimizes the design according to user design constraints. Constraint entry is enabled and simplified by the graphical user interface (LDC Editor), which extracts and displays all the relevant design information so user can quickly specify accurate design constraints. The constraints convey performance requirements and optimization options to the optimization engines. Users can view and analyze their design as a schematic using the Netlist Analyzer tool. This is an effective way to quickly analyze the post-synthesis results.
After the optimization process is complete, LSE generates a netlist ready for Map, and Place & Route steps of the FPGA design flow. LSE generates the output in ngd format, which is a fully complete netlist (no black boxes). The option of generating an EDIF netlist is also available. LSE is tightly integrated within the Lattice Diamond environment, making it simple and easy to use.
LSE has been developed and validated for many years. It was first publically released in Diamond 1.1 on November 8, 2010 as beta for Lattice MachXO & MachXO2 devices. The tool has been continuously tested and refined by the internal QA & Applications, and customers over each subsequent Diamond and iCEcube2 release. Since 2008, LSE has been tested and validated with numerous design suites such as basic logic cases, standard benchmark suites, communication prototypes, board demos and IPs. LSE has shown consistently excellent results on XO/XO2 benchmarking suites. Over the last couple of years multiple field evaluations were launched with LSE to increase customer usage. In the process, many customer designs have been collected, tested and included in Lattice internal benchmarking. Currently more than 20,000 unit test cases are run with LSE to validate QoR and functional verification on weekly basis.
Operating System Support
- Windows XP 32-bit
- Windows Vista 32-bit
- Windows 7 32-bit & 64-bit
- Redhat 4, 5, 6 32-bit & 64-bit
- 64-bit; SUSE 10.1 32-bit
- Verilog 95 and 2001 IEEE-1364 Std
- VHDL 87 and 93 IEEE 1076 Std
- Mixed-HDL support
Synthesis and Optimizations
- Optimizations for:
- Timing driven synthesis optimization
- Embedded static timing analysis
- ECP5 device family (Lattice Diamond software)
- Lattice MachXO3L device family (Lattice Diamond software)
- Lattice MachXO2 device family (Lattice Diamond software)
- Lattice MachXO device family (Lattice Diamond software)
- Lattice iCE40 device family (Lattice iCEcube2 software)
- Fully integrated in Lattice Diamond® and iCEcube2 design software
- Tcl extensions for scripting
SDC Supported Constraints
- create_clock: clock definition
- create_clock –name name –period [clock port|net]
- set_input_delay: input setup time requirement
- set_input_delay -clock [clock port|net] [portlist]
- set_output_delay: clock to output requirement
- set_output_delay -clock [clock port|net] [portlist]
- set_max_delay: max delay requirement for a path
- set_max_delay -from [port|cell] -to [port|cell]
- set_multicycle_path: multicycle path definition
- set_multicycle_path -from [net|cell] –to [net|cell]
- set_false_path: false path definition
- set_false_path -from [port|cell] -to [port|cell]
- Set_false_path –through [net]
HDL Supported Attributes and Directives
- synthesis: a text macro used with Verilog ‘ifdef directive
- translate_off/translate_on: instruct LSE to ignore codes between these 2 directives
- black_box_pad_pin: specify PIOs of a black box
- syn_black_box: instruct LSE to treat a module/component as a black box
- syn_keep: instruct LSE to preserve the specified net without optimizing it away
- syn_noprune: prevents instance optimization for black boxes with unused output ports
- syn_preserve: prevents sequential optimization such as FSM extraction, etc.
- loc: specify pin location
- syn_encoding: VHDL enumerated data type encoding style; support 1-hot, gray and binary
- syn_hier: control the amount of hierarchical transformation
- syn_maxfan: control fanout of a port net or registered output
- syn_ramstyle: specify RAM implementation style; support registers, distributed RAM, block RAM
- syn_romstyle: specify ROM implementation style; support distributed ROM and EBR
- syn_useioff: specify whether use I/O registers
- syn_use_carry_chain: specify whether use carry chain for adders
(For more details, please check out Online Help.)
- Carry Chain Length
- Maximum # of output bits mapped to a single carry chain
- EBR Utilization
- Target percentage of EBR utilization
- FSM Encoding Style
- Support 1-hot, Gray and Binary
- Force GSR
- Use global set/reset resources
- MUX Style
- Support L6Mux Multiple, L6Mux Single and PFU Mux
- Max Fanout Limit
- Maximum number of fanouts limiting to the value.
- Propagate Constants
- Allow LSE to propagate constant wherever possible to reduce area
- RAM Style
- Support embedded block RAM, distributed and registers
- ROM Style
- Remove Duplicated Registers
- Eliminate the duplicate Flops
- Resource Sharing
- Option to turn of resource restructuring around arithmetic operators.
- Use Carry Chain
- Controls the usage of dedicated carry chains for arithmetic operators.
- Use IO Insertion
- Enable/Disable IO insertion
- Use IO Registers
- User control to pack registers in IO pads
- Optimization Goal
- Target Frequency (MHz)
- Number of Critical Paths
- # of critical paths to be reported
- Hardware Evaluation
- Enable/disable IP evaluation capability
- Macro Search Path
- Paths to physical macro files
- Memory Initial Value File Search Path
- Paths to memory initialization file
- Remove LOC Properties
- Removes LOC properties in synthesized design
- Resolved mixed drivers
- Resolve mixed VCC & GND drivers
- Output Preference File
- Carry LDC constraints to LPF
LSE Usage Guidelines for Lattice Diamond
- In general, using Area mode is always a good start point
- Suitable for most designs
- Default strategy settings are sufficient
- Timing constraints (SDC) are unnecessary (ignored)
- If Fmax reported by PAR TRACE doesn't meet requirement, try the next mode
- Use Balance mode, this usually yields better Fmax than Area mode with increased area (LUT)
- Timing constraints (SDC) are not required
- Default strategy settings are sufficient
- Use Timing mode if the other two modes do not produce desired results
- Designer needs to supply appropriate clock and other timing constraints
- Yields smaller design (LUT) with correct constraints than if not constrained or over constrained
- Over constraining is unnecessary and not recommended