Updated MachXO3L/LF Device Support
- Enable placing I/Os of different voltages into the same I/O bank. This can enable higher pin utilization and more flexibility for board design.
- Support of datasheet update for approx. +10% voltage range on 3.3 V I/O. Note: feature same as XO2.
- 900 MBps MIPI support. See MachXO3 Data Sheet. Above 800 Mbps is only supported in WLCSP and csfBGA packages.
- Direct migration of design from LF to L for user cost reduction. Design can now be migrated without re-compile so all timing is preserved.
- With the L and LF variants, the location of the golden bitstream for “dual boot” could potentially be in the internal (NVCM) or external (SPI) memory. Now user has the option to choose between either location, although with L variant, the most likely location will be internal as the internal location is NVCM and therefore not programmable for as many cycles.
Clarity Designer Tool (ECP5 only)
- Support of “single module” mode to reduce user steps required when generating only a single module to be included in the design.
SEI Editor Tool – this tool, used to create single event errors to an operating device for system testing, is now also supported for MachXO2, MachXO3L/LF
Netlist Analyzer Tool (used with Lattice Synthesis Engine (LSE))
- Various enhancements to improve ease of use:
- Easily access the design’s clock sources using new sub-group for clocks
- Cleaner schematics by collapsing scalar signals on Lattice primitives to bus form
- Find high fanout nets in the Find dialog by sorting by fanout
- Support of bookmarks in schematic to easily recreate views
Lattice Synthesis Engine
- Always honors defined timing constraints, regardless of the LSE tool setting for Optimization Goal (Area, Balanced, or Timing).
- Added support for Windows 8.1
Synopsys SynplifyPro Synthesis update: to version J-2015.03L-SP1
Aldec Active-HDL Simulation no change (version 10.2)