Diamond Version History

Diamond Version 3.9

  • CrossLink Family Support - Power Calculator enhancements for more precise data for both normal and sleep mode operations
  • ECP5UM5G Family Support
    • Soft Error Injection (SEI) and LatticeMico support.
    • SERDES parameters tuning for optimal performance.
  • ECP5U/UM Family Support
    • ECP5U-12K plus ASC, ECP5UM-25K/45K plus ASC device support
    • SERDES parameters tuning for optimal performance.
  • MachXO2 Family Support - MachXO2HE devices with ASC device are generally available.
  • MachXO3LF Family Support
    • MachXO3LF packages with ASC device is generally available.
    • Package, Timing, SSO and IBIS hardware data files are in final status
  • MachXO3L/LF & MachXO2 - INBUF support - All input buffers of unused PIO and used outputs are disabled to save power when INBUF is set to OFF
  • Deployment Tool - Support added for STAPL file generation for ASC devices.
  • Diamond Programmer - Macronix SPI flash device support added to Diamond Programmer.
  • LatticeMico - Starting from Diamond 3.9, the LatticeMico installer will be starting from version 1.0 and remain until updates are made to LatticeMico

Diamond Version 3.8

  • Software support for
    • CrossLink (LIFMD) devices, the first programmable ASSP interface bridges for mobile image sensors and displays that support a variety of interfaces such as MIPI D-PHY, CSI-2, MIPI DSI/DPI, CMOS SubLVDS, LVDS, etc.
    • ECP5-5G device family, supporting 5G SERDES and up to 85K LUTs in small packages
    • ECP5 12K device, extending current ECP5 device family to include 12K LUTs
    • MachXO3 9400 device, extending current MachXO3 device family to include 9400 LUTs.
    • MachXO2 256/640 48-pin QFN package
  • Soft Error Injection (SEI) editor support for MachXO2 and MachXO3 device families

Diamond Version 3.7

  • MachXO2 and MachXO3 – MachXO2 and MachXO3L/LF support lower voltage input and bidirectional I/O types (LVCMOS10R25, LVCMOS10R33, LVCMOS12R25, and LVCMOS12R33).
  • MachXO2 QFN32 package is generally available.
  • ECP5U Family Support – ECP5U 12K device support has been added.
  • Place and Route – PAD Report has been enhanced to add shared sysConfig pins and dedicated sysConfig pins.
  • Programmer – Added Programming Speed Settings to Cable Settings tab.
  • Security Setting Tool – Security Setting Tool now supports MachXO2 and MachXO3L devices.
  • Soft Error Injection (SEI) Editor – SEI Editor now supports MachXO2 and MachXO3L/LF devices using JTAG.

Diamond Version 3.6

Updated MachXO3L/LF Device Support

  • Enable placing I/Os of different voltages into the same I/O bank. This can enable higher pin utilization and more flexibility for board design.
  • Support of datasheet update for approx. +10% voltage range on 3.3 V I/O. Note: feature same as XO2.
  • 900 MBps MIPI support. See MachXO3 Data Sheet. Above 800 Mbps is only supported in WLCSP and csfBGA packages.
  • Direct migration of design from LF to L for user cost reduction. Design can now be migrated without re-compile so all timing is preserved.
  • With the L and LF variants, the location of the golden bitstream for “dual boot” could potentially be in the internal (NVCM) or external (SPI) memory. Now user has the option to choose between either location, although with L variant, the most likely location will be internal as the internal location is NVCM and therefore not programmable for as many cycles.

Clarity Designer Tool (ECP5 only)

  • Support of “single module” mode to reduce user steps required when generating only a single module to be included in the design.

SEI Editor Tool – this tool, used to create single event errors to an operating device for system testing, is now also supported for MachXO2, MachXO3L/LF

Netlist Analyzer Tool (used with Lattice Synthesis Engine (LSE))

  • Various enhancements to improve ease of use:
    • Easily access the design’s clock sources using new sub-group for clocks
    • Cleaner schematics by collapsing scalar signals on Lattice primitives to bus form
    • Find high fanout nets in the Find dialog by sorting by fanout
    • Support of bookmarks in schematic to easily recreate views

Lattice Synthesis Engine

  • Always honors defined timing constraints, regardless of the LSE tool setting for Optimization Goal (Area, Balanced, or Timing).

OS Support

  • Added support for Windows 8.1

Synopsys SynplifyPro Synthesis update: to version J-2015.03L-SP1

Aldec Active-HDL Simulation no change (version 10.2)

Diamond Version 3.5.1

Enhancements to ECP5 Support

  • Improved performance and function for all Lattice IP that use the ECP5 SERDES. Highly recommended for users of: SGMII/GbE PCS, XAUI, PCIe, PCIe Root Complex Lite, CPRI, JESD204B
  • Improved clock resource allocation enabling easier design fitting for designs with multiple clocks
  • Fix an issue in VHDL flow on HDL generated by Clarity tool

This update is highly recommended for ECP5 users.

Diamond Version 3.5

New Device Support

  • ECP5 family access using standard Diamond user licenses
    • ECP5U (non-serdes): Free or Subscription license
    • ECP5UM (serdes): Subscription License

Clarity Designer Tool (ECP5 only)

  • Planner – enable un-placement of individual ports, rather than the entire interface.

SEI Editor Tool (ECP5 only) – this is a new tool used to create single event errors to an operating ECP5 for system testing (general access)

Lattice Synthesis Engine (LSE)

  • Support added for 4 Diamond FPGA families. LSE will be selected for the synthesis tool, by default, for new projects targeting these families. Existing projects will continue to use the synthesis tool previously used by that project.
    • LatticeECP2, LatticeECP2M
    • LatticeECP3
    • LatticeXP2
    • Note – families previously supported: MachXO, MachXO2, MachXO3L, ECP5
  • Feature addition: support of non-zero initialization of register
  • Continued improvements to the Netlist Analyzer. For example:
    • Enhanced performance of major commands: filter, expand, flatten
    • Enhance cross probe from post-MAP view to Technology view, improving accuracy
    • Enhance “property dialog” and “tooltip”, displaying parameter information and correct fan-outs number for nets
  • Updated HDL attributes: support of syn_encoding = “safe”

Diamond Programmer

  • Add Diamond Deployment Tool hex conversion options
  • Updates to device programming
    • General access to ECP5

Synopsys SynplifyPro Synthesis update: to version J-2015.03L

Aldec Active-HDL Simulation no change (version 10.1)

Diamond Version 3.4.1

  • Early access program support for MachXO3LF devices
  • To support PB1412 I2C readback issue: added new I2C Recovery Erase operation to Programmer, and DRC for presence of EFB/WB clock

Lattice Diamond 3.4

  • New Device Support
    • Support added for ECP5-85 U/UM devices. Adds to existing support of ECP5-85-ES U/UM devices
    • XO3L – general support for the csfBGA packages (121, 256, 324 pin). Very important to use D3.4 for these packages to get final pinout information.
    • XO2 – 7K/4K – addition of the caBGA400 package (controlled access).
    • XO2HC now supports up to +10% voltage. Tools such as Power Calculator, Spreadsheet View & Preferences, Trace analysis have been updated.
  • Clarity Designer Tool (ECP5 only)
    • Builder – the schematic view has added drag and drop functionality to connect available components, ports and pins to other components, ports and pins. See online help topic: Building With Schematic View
    • Planner – the planning tab now has a Usage report that allows you to monitor the resource usage during the planning task. The report is updated after each planning operation – showing the used and total available resources
  • SEI Editor Tool (ECP5 only) – this is a new tool used to create single event errors to an operating ECP5 for system testing (controlled access)
  • Lattice Synthesis Engine (LSE)
    • Updated SDC constraints:
      • create_clock: can specify when the clock’s rising and falling edges happen during clock period (-waveform)
      • create_generated_clock: can specify a duty cycle as a percentage of the clock period (-duty_cycle)
      • set_clock_groups: can have multiple clocks in a group
      • set_input_delay and set_output_delay: can specify that the delay value refers to the shortest or longest path (-min, -max)
      • set_min_delay: is a new constraint that specifies the minimum delay for the timing paths.
    • Many improvements to the Netlist Analyzer. For example:
      • Added post-MAP view. This is not available in the Synplify Pro flow.
      • Cross probing between open RTL, Technology and post-MAP Views. As Trace report makes many references to post-MAP netlist, user can gain more insight into the source of timing issues by visually seeing them in the post-MAP view.
      • Improved Find feature
    • Updated HDL attributes: Support for HDL attributes for IO configuration (e.g. IO_TYPE, SLEWRATE). Further eases migration of some designs to LSE.
  • Diamond Programmer
    • Programming enabled for ECP5-45
  • OS support – Removal of support for Windows XP and Vista
  • Synopsys SynplifyPro Synthesis update: to version J-2014.09L
  • Aldec Active-HDL Simulation no change (version 9.3sp1)

Lattice Diamond 3.3

  • Windows 8 support
  • Lattice Synthesis Engine (LSE) expanded support for the following family of devices:
    • ECP5 devices
  • Controlled support for XO3L devices in csfBGA packages (121, 256, 324 pin). Targeting a design to any of these packages in Diamond 3.3 release has certain risks as these products will change in the future. Contact techsupport for more information and to request access
  • Note that the XO3L csfBGA pinouts are being re-designed. Designing to these packages in Diamond 3.3 has risks as the pinouts will change significantly
  • IPexpress now supports MIPI D-PHY for XO2/XO3L. IPexpress enables user to quickly create transmit or receive MIPI interfaces. These interfaces can either support both high speed and low power lanes, or to reduce IO, support high speed lane only. Pin/Pad reports more clearly show which IOs are for MIPI to support board design. See technote TN1202, TN1203 for more details on implementing MIPI D-PHY on XO2 and TN1280 & TN1281 for XO3L
  • LSE expanded support for Netlist Analyzer, a tool that allows users to view the pre-synthesis (RTL) and post-synthesis version of their design as a schematic. This feature allows users to preview or review their designs when LSE is chosen
  • LSE expanded support for synthesis attributes such as full_case, parallel_case, syn_enum_encoding, and syn_sharing
  • Clarity Designer expanded support for Virtual VCCIO for DDR memory. Virtual VCCIO improves interface speed by lowering SSO effect. When using Clarity Planner to assign DDR memory pins, the Virtual VCCIOs will be automatically placed in the correct locations within each DQS group for ease of use
  • Clarity Builder now supports block connections using schematic tool for connecting design blocks together.
  • Diamond Programmer
    • Support for new FTDI cable (HW-USBN-2B) and the ability to upgrade the cable firmware.
    • Now includes device database version in log file
    • Support for iCE40 Ultra (iCE5LP) devices without license control
  • Deployment Tool
    • Supports SPI Flash read mode for external memory and dual boot options for ECP5
    • Added support for 512Mb SPI Flash
    • Removed ECP5 Quad I/O SPI Flash support for external memory
    • Includes device database in log file
    • Support iCE40 Ultra (iCE5LP) devices without license control
  • The File List can now show Reveal Analyzer files (.rva) in addition to Reveal Inserter files (.rvl) in the Debug Files folder. Each rva file will show which rvl file it is associated with in the list
  • Platform Designer now supports PMBus Adapter component. The PMBus Adapter, while being compatible with PMBus standard 1.2, also supports sophisticated power sequencing as well as PMBus 1.3 features such as automatic voltage scaling, very fast fault detection etc. A PMBus controller can now manage all analog supplies on the board by using standard PMBus commands. Designers can now iterate through power sequencing without modifying the PMBus controller firmware
  • Diamond online help now supported on Chrome Browser
  • Improved Search capabilities for Diamond help
    • New toolbar for simultaneous access to index, content, and search subpages in the same web location. With this capability, the state of the subpages are preserved for ease of reading
    • Search box in the toolbar
    • Search while you type: The list of hits appears and is modified in the search page while user is typing for faster results
    • Search results have context: Each search hit includes the first few lines of the topic to help you decide if the topic is relevant to your question
    • Search results re-organized: Hits from all the books are listed in relevance order, thereby increasing the likelihood that the first few hits are the most relevant
    • Search allows the use of quotation marks can be used for specific strings

Lattice Diamond 3.2

  • Adds support for all ECP5 devices
  • Clarity Designer is a new tool with improved design entry methods to allow creating, connecting, and placing systems (ECP5 support only)
  • Reveal support for ECP5 SERDES debug for hardware debugging assistance
  • Adds support for all MachXO3L devices
  • GDDR x4 support in MachXO3L for implementation of high speed interfaces while running core frequency at slower rate such as MIPI D-PHY and subLVDS.
  • LatticeMico System support in MachXO3L for embedded design development.
  • Adds support for MachXO2 LCMXO2-2000ZE in WLCSP49 package.
  • Lattice Synthesis Engine (LSE) expanded support for the following family of devices:
    • MachXO3L device
    • ECP5 devices (pure HDL designs only)
  • LSE expanded to support Synopsis Design Constraints (SDC) for commonly used timing constraints. This facilitates timing constraint entry for users who preferred to use SDC based timing constraints.
  • LSE expanded to support various Synplify Pro's synthesis attributes. This allows users to migrate existing Synplify Pro based design to LSE with minimal rewriting of attributes.
  • Enhanced the Auto Hold Correction algorithm. With the new algorithm, designs with zero setup timing score are more likely to have their hold violations fixed. Furthermore after hold correction, the setup timing score should remain at zero. This feature helps user by increasing the yield of usable designs.
  • Enhanced handling of HDL attributes and edits in Spreadsheet View. The enhancement follows the rule that constraints entered in LPF override those entered in HDL flow.
  • If Synopsys Design Constraints (SDC) are used for synthesis, they can now be automatically translated to LPF language and used in the MAP/PAR process. The LPF file created to accomplish this is not visible from Diamond but the constraints can be seen from SpreadSheet View (SSV) much like HDL attributes can be seen from SSV. Automatically using SDC in MAP/PAR is the default behavior in new projects, but not in existing projects. This feature is enabled/disabled through the synthesis strategy setting: “Use LPF Created from SDC in Project” (both LSE and Synplify). This feature provides a single entry point for timing constraints and can help manage preferences that must be defined on nets.
  • ECO editor log information persists. This allows users to the the log information after closing and reopening the window.
  • Messaging System Enhancements
  • Diamond Programmer Enhancements
  • Deployment Tool Enhancements
  • Programming File Utility Enhancements
  • Model 300 Utility Enhancements
  • Platform Designer Enhancements
    • Updates to VMON table, IMON table, VID IP, and I2C slave address
    • Additional Hot swap support
  • Synopsys Synplify Pro has been updated to version I-2013.09L-SP1-1
  • Aldec Active-HDL LE II has been updated to version 9.3

Lattice Diamond 3.1

  • New device support for select MachXO3 devices (LCMXO3L-2100C caBGA256, LCMXO3L-4300C caBGA256, and LCMXO3L-6900C caBGA256).
  • Lattice Synthesis Engine (LSE) now supports MachXO3 devices.
  • Cloning an existing Diamond Project is now possible by using “Save As…” command. So users can copy a Diamond Project to a different name.
  • Power Calculator has been enhanced with more accurate estimation of the clock network’s power consumption.
  • Programmer now includes full support for iCE40LM devices.
  • Programmer now has Configuration Options Settings. So users can select different device configuration options without having to regenerate a data file.
  • The Programming File Utility now has a Feature Row Editor. This editor provides visual information of the data file’s fuse settings so that users can easily edit the data file to enable or disable silicon features in MachXO2 devices.
  • Reveal Analyzer now supports sample clocks as slow as the JTAG clock speed. This lower frequency increases the range of the sampling clock to a lower minimum from a minimum of 3X of JTAG clock speed.
  • USB driver for Windows OS has been certified by Microsoft.
  • With the user’s permission, Diamond can now collect and send to Lattice via the internet (only) the WARNING and ERROR messages encountered by the user. This information enables Lattice to improve the users experience.
  • Platform Designer has a “Buffer XO2 outputs for ASC synchronization” option, which adds one register delay from LogiBuilder output to MachXO2 devices’ pins. This option allows users to choose whether ASC and XO2 output signals appear at the same cycle.
  • Platform Designer now includes a User Configurable Hot Swap feature for Platform Manager 2 and ASC devices.
  • Synopsys Synplify Pro has been updated to version I-2013.09L
  • Aldec Active-HDL LE II has been updated to version 9.3

Lattice Diamond 3.0

  • New device support for Platform Manager 2 and companion ASC devices.
  • New message system outputs messages from the implementation engines into the Report View. These messages can now be filtered and sorted to allow users to manage and understand messages better.
  • Platform Designer is a new tool that provides the ability to create and control a complete hardware system using Platform Manager 2 or MachXO2 devices.
  • New option in the file list to allow implementations to be cloned within a project.
  • System Verilog files are now supported in the file list and can be used for implementation. System Verilog files are not supported in LSE, Hierarchy View, HDL Diagram, Simulation Wizard, or Reveal Debugger.
  • Programming File Utility is a new standalone tool that allows programming files to be view and compared.
  • Model 300 Programmer is a new standalone tool that supports the Lattice Model 300 Programmer hardware.
  • Reveal Debugger now supports monitoring power-on reset (POR) functions which happen immediately after powe-on of the hardware.
  • Report View now includes a Tcl commands log in addition to the new messaging system functionality.
  • Spreadsheet View now displays the rows of ports and pins in categorized groups.
  • Run Manager now shows additional information on worst-case slack and timing scores.
  • Synopsys Synplify Pro has been updated to version H-2013.03L
  • Aldec Active-HDL LE II has been updated to version 9.2sp1.

Lattice Diamond 2.2

  • Adds support for MachXO2-4000HE with csBGA184 package.
  • Adds support for LatticeECP3-17 and LatticeECP3-35 automotive grade (LAE3) devices.
  • Online help has updated content for schematic entry.
  • Deployment Tools now supports generating warm boot and cold boot hex files for iCE40 devices when used in standalone mode.
  • IPexpress includes updates for Adder Tree, FFT_Butterfly, Multiply_Add_Sub, and Sin-Cos_Table modules.
  • Strategies now include a new option for VHDL 2008 support in Synplify Pro.
  • LatticeMico System includes a new preprocessor option for LatticeMico EFB for MachXO2 for optimizing code size.
  • Lattice Synthesis Engine (LSE) synthesis tool has been updated.
  • Synopsys® Synplify Pro® for Lattice synthesis tool has been updated with version G-2012.09L-SP1.
  • Active-HDL Lattice Edition II from Aldec was updated to version 9.2sp1.

Lattice Diamond 2.1

  • Lattice Diamond 2.1 is now available as a Linux 64-bit application for RHEL 4, 5, and 6.
  • TRACE and Timing Analysis view now group unconstrained paths by type.
  • TRACE and Timing Analysis view report path details on paths covered by BLOCK preferences.
  • Download Debugger is a new stand-alone software tool for debugging Serial Vector Format (SVF) files, Standard Test And Programming Language (STAPL) files, and Lattice Embedded (VME) files. Debugger allows you to program a device, and edit, debug, and trace the process of SVF, STAPL, and VME files.
  • Lattice Diamond tutorial has been updated with additional content and now supports the ECP3 Versa Development Board
  • The online FPGA Design Guide has a new chapter, HDL Coding Guidelines, which provides VHDL and Verilog design guidelines to help you achieve the best results.
  • The Hierarchy view opens automatically when you open a project. This allows the hierarchy of the design to automatically be shown, preventing confusion on how to show this information.
  • IPexpress shows compatiblity of IP modules with the version of Diamond that you are running by displaying different icons for supported, unsupported, and incompatible versions.
  • LatticeMico™ System include updates to many of it's components including LatticeMico32 microprocessor, and LatticeMico8 microcontroller. See the included documentation for complete details. Additionally LatticeMico™ System allows the generation of platform without a processor and has a new option to significantly improve download speeds of application images.
  • The Place And Route (PAR) report now includes a worst slack value for each place-and-route run. This is the worst timing slack for all timing constraints. Negative values indicate timing violations. You can use this value instead of the timing score to judge the overall timing quality of a run.
  • Multi-seed PAR runs (multi-PAR) now automatically terminate individual runs that do not show improved results over already completed runs. This will normally result in a significant speedup of the total runtime.
  • Diamond Programmer has been updated with several new features:
    • Support has been added for non-Lattice JTAG-ISC and JTAG-STAPL devices.
    • A Custom Device Database has been added, allowing you to add non-Lattice JTAG devices to the device database. This allows Programmer to scan these devices.
    • A Cable Signal Test feature has been added to allow debugging JTAG connections.
    • The Slave SPI Embedded was updated to support SPI Flash programming through the FPGA.
  • Power Calculator has added several new features
    • Power Matrix page shows the amount of power pulled by each component in the design from multiple power sources.
    • Implementation Comparison table compares power consumption among multiple implementations of a design.
    • Average power and thermal comparison table for low-power devices shows an estimate of average power used over time for standby, full power, and shutdown modes.
    • Comparison chart of power awareness for low-power devices compares the amount of power used in standby mode and non-standby mode.
  • Reveal Inserter now parses mixed Verilog and VHDL designs and displays the signal names at the RTL level instead of the netlist (EDIF) level.
  • Simulation Wizard has been improved to allow you to automatically add top level signals to the waveform and then run the simulation.
  • Bitstream file generation for MachXO2 is now supported in addition to JEDEC file generation within the process view.
  • Synopsys® Synplify Pro® for Lattice synthesis tool has been updated, with version G-2012.09L.
  • Active-HDL Lattice Edition II from Aldec was updated to version 9.2.

Lattice Diamond 2.0.1

  • Lattice Diamond 2.0.1 removes the support for LatticeECP4 devices.
  • Diamond Programmer 2.0.1 can be used to configure and program Lattice iCE40 devices. All current iCE40 products/packages are supported for all programming modes (NVCM, SRAM Configuration and External FLASH Programming).
  • Now suport for the ispLEVER Classic and iCE devices has been added to the Aldec® Active-HDL™ Lattice Edition libraries in Diamond. So, if you need to simulate multiple designs targeted to devices available in different software products (e.g. XO, 4KZE, and iCE), please use the Active-HDL version provided with Diamond 2.0.1.
  • With this update, Lattice Diamond has improved timing simulation support for a LatticeECP3 design that includes DDR2 or DDR3 memory interfaces.
  • Improvements to the Schematic Editor have been added, in particular improving zooming of a multi-page schematic and helping with the selection of library components.

Lattice Diamond 2.0

  • Trace Report now includes an improved, unconstrained paths section so users can more quickly identify and fill gaps in their design constraints.
  • With Diamond Programmer 2.0, users can add their own SPI Flash devices directly in the release allowing faster support for these devices.
  • Lattice Diamond Deployment Tool 2.0 also offers improved functionality including file conversion, external memory file generation, improved I2C embedded for the MachXO2 devices and Slave SPI for the LatticeECP3 and LatticeXP2 devices.
  • Stand-alone Power Estimator is now available for power estimation of all devices (including LatticeECP3). It doesn’t require a Diamond Installation; however it requires a free Lattice Diamond license.
  • The FPGA design guide has been revised. Two sections are provided and linked on the start page of the software: Timing Closure and Design Planning.
  • To provide consistent tool behavior from release to release, strategies now include and save all values, not just non-default values, since the default can change from release to release. In a similar fashion, default preferences are saved explicitly when exporting all Spreadsheet Preferences to LPF. This new method can help avoid some of unexpected changes found when upgrading to a new release.
  • The default Router is now Negotiation-Based Router (NBR). It provides about 20 to 30% runtme improvement over CDR, however it requires more CPU memory.
  • A new, partition-based incremental design flow for LatticeECP3™ and LatticeECP2/M FPGA devices will help preserve design performance and reduce run time after a design change is made.
  • In addition to the 32-bit application for Windows XP and Vista, Lattice Diamond 2.0 software is now also provided as a 64-bit application for Windows 7 to increase memory capacity to support larger devices. For Linux users, Lattice Diamond 2.0 now runs on Linux Red Hat 6 in addition to versions 5 and 4.
  • Synopsys® Synplify Pro® for Lattice synthesis tool has been updated, with version F-2012.03L.
  • Active-HDL Lattice Edition II from Aldec was updated to version 9.1.

Lattice Diamond 1.4.2

  • Lattice Diamond 1.4.2 is an update to Lattice Diamond 1.4. Before installing this update, please install version 1.4 of Lattice Diamond.
  • Lattice Diamond 1.4.2 addresses an issue found in Lattice Diamond 1.4, where a design targeted to a LatticeECP3 Low Power FPGA (-6L, -7L or -8L) may not show the same timing performance as the regular LatticeECP3 FPGA (the non -L or-6, -7,-8) as expected.
  • With this update, support is added for the new 32QFN package of the 256 MachXO2 device and support for MachXO2 WLCSP-49 device has been removed.
  • The IPexpress tool EFB module graphical user interface (GUI) now has Wishbone checkbox that allows the user to provide access to embedded flash memories in all MachXO2 devices, without instantiating un-needed interfaces like I2C and SPI
  • For MachXO2, the UFM/Configuration I2C slave address is clearly displayed in the IPexpress EFB module I2C Configuration tab and in the Map report.
  • For MachXO2, the keyword MUX_CONFIGURATION_PORTS has been added to the sysCONFIG preference. This feature allows all Configuration ports to be disabled in order to provide additional user I/Os. It can be set to ENABLE or DISABLE in Diamond’s Spreadsheet View or manually in the logical preference file.
  • The Soft Error Detect (SED) during normal active operation has been removed from LatticeXP2 and LatticeECP2/M devices. Refer to PCN 02B-12 Notification of a Revision to the LatticeXP2, LA-LatticeXP2 and LatticeECP2/M Data Sheets. The SED function can still run on a programmed device when the user logic is inactive.

Lattice Diamond 1.4

  • Lattice Diamond 1.4 software provides final timing and power analysis device information, as well as final production package, bit stream data based on the actual silicon characterization for all the MachXO2 devices.
    • The final simultaneous switching output (SSO) data is available for all packages except for the wafer-level chip scale package of the LCMXO2-2000U that will be provided later
    • The quality of results (QoR) is at par with what was obtained with version 1.3 on most designs targeted to the LCMXO2 devices
  • To get timing closure faster, users can now use a new PAR strategy setting “Stop Once Timing is Met” to get multi-PAR to stop after either trying a maximum number of seeds or when the last seed run has resulted in a timing score of zero – whichever comes first.
  • LSE users can now create and edit Synopsys Design Compiler (SDC) synthesis constraints in the new Lattice Design Constraints graphical editor. This editor automatically populates design clock, port and net names and provides real time syntax and semantic checks. It generates an SDC file that can be used with LSE.
  • With this release comes the new Diamond Deployment Tool. It uses an intuitive wizard approach to create the appropriate device programming file in the format required by the user’s deployment method. Diamond Deployment Tool is a standalone tool available as an accessory in the Lattice Diamond environment.
  • With Lattice Diamond 1.4, users can pause, stop and resume per seed, any of the multi-PAR jobs run under Run Manager. They can export the results in a CSV file, and they can also compare run reports of multiple implementations side by side and easily determine the best implementation for their design.
  • Using Run Manager, users can individually control the maximum number of implementations and multi-PAR processes that can be run simultaneously. Parallel processing is only supported on a single computer with a multi-core CPU. Parallel processing across multiple computers is not currently supported.
  • Lattice Diamond will help users migrate their designs to a lower cost device within the same device family while preserving the current package and board layout. This capability has now been extended to all the Lattice device families supported by Lattice Diamond software. Users are provided pin migration information in the Package view and Spreadsheet views, such as incompatible pins. This pin migration information can also be exported to the Pin Layout file.
  • Lattice Diamond 1.4 software now displays in the hierarchy view resources used by each level of design hierarchy following either the synthesis or the map step. Device resources can therefore be displayed as both logical (registers) and physical (slices) elements. This feature helps users quickly understand what parts of their design are using scarce device resources so that they can optimize the design for the targeted device. This information can now also be exported to a text or a CSV file to enable analysis in other tools.
  • With this release, the pin assignment Design Rule Check (DRC) engine has been redesigned and implemented for the LatticeECP3™, MachXO2 and LatticeSC™ device families to provide real-time as well as on-demand DRC during pin assignment and configuration, and a user-friendly report helps identify and correct pin usage issues.
  • Users can now insert an unlimited number of custom columns in Port and/or Pin Assignments tabs of Spreadsheet View. User can use these columns to comment/document per port or pin. The order of the column can be changed via drag and drop. The information can be exported to or imported from a Pin Layout File. It will not be included in LPF files and will not affect the processing.
  • With this release of Reveal, Token Manager was moved from Reveal Inserter to Reveal Analyzer. This allows tokens to be changed without re-inserting debug and resetting the process list. However it doesn’t allow tokens to be defined before running Analyzer.
  • Synopsys® Synplify Pro® for Lattice synthesis tool has been updated, with version F-2011.09L, released in September 2011.
  • Active-HDL Lattice Edition II from Aldec was updated to version 8.3SP1.

Lattice Diamond 1.3.1

  • Lattice Diamond 1.3.1 is an update to Lattice Diamond 1.3. Before installing this update, please install version 1.3 of Lattice Diamond.
  • Lattice Diamond 1.3.1 adds support to the 328 csBGA 10x10mm, 0.5 mm pitch wire bonded package for the LatticeECP3 17K devices with both industrial and commercial grading.
  • There are improvements made to Reveal in Diamond 1.3.1 to address three issues:
    • In some cases with Lattice Diamond 1.3, the waveform output is not correct when using 3 TUs and having a Max Sequence Depth of Trigger Expression (TE) set to 4.
    • In some cases, when using LatticeECP3 distributed DP RAM, Reveal would fail with a “circuit has too large data_width” error message.
    • The Inserter GUI sometimes reports "Catch unknown exception".

Lattice Diamond 1.3

  • Lattice Diamond 1.3 software provides updated timing and power analysis device information, as well as final production package, bit stream and SSO analysis data based on the actual silicon characterization for the MachXO2 LCMXO2-1200 and LCMXO2-1200U devices.
  • These changes, plus ongoing improvements to the synthesis, MAP and PAR implementation engines, have resulted in an FMax improvement of 5% to 15% on most designs targeted to the LCMXO2 devices.
  • Lattice Diamond 1.3 adds support for a wafer-level package for the LCMXO2-2000U that is needed for very high volume, cost sensitive applications.
  • Lattice Diamond 1.3 software provides device resource utilization for each logical level of the design hierarchy following synthesis, and enables users to make early design decisions about how to structure their design so that they can optimize utilization of the overall device.
  • Designers can add user-defined clock jitter to their design’s clocks while they are performing static timing analysis of these designs. Users control the amount of clock jitter through an extension to the existing Trace timing preferences, and see the analysis results in both the Trace report and the Timing Analysis View.
  • Software provides features to help migrate a design to a lower cost device while preserving the current package and board layout. This capability is available for MachXO2 and LatticeECP3 devices. Users get incompatible pin information in the Package View and Spreadsheet View. This pin migration information can also be exported to the Pin Layout file.
  • Projects can now support complex multi-file test benches and allow multiple design representations for the same design block (such as for synthesis and a different one for simulation).
  • The simulation wizard can automatically determine which files should be set to simulation and pass the correct options to the simulator.
  • The synthesis design constraints flow allows for multiple files (SDC and/or LDC files) that can be managed similar to the back-end preference files (LPF files).
  • Using Reveal Analyzer, users can now download large trace data amounts and configure complex trigger setups more than 10 times faster than previously possible.
  • With Diamond Programmer, users can program the devices from within Diamond in a much easier way than ispVM for the most common steps such as setting up the cable, scanning the board, and direct programming of the device.
  • Users can directly select the active implementation in Run Manager and also control which one of the multi-par runs is used so that the rest of the design flow can be focused on the implementation that provides the best placement and routing run for that design.
  • Lattice Diamond 1.3 supports the Platform Manager devices
  • Users can manage, document and export the information about the package pin out for early pin planning and pin assignment exchange with PCB designers and/or third party tools for pin assignment signoff and design document. Users can get a device's package pin information right from within Diamond

Lattice Diamond 1.2

  • MachXO2 users can now generate complete systems based on the LatticeMico8™ open-source 8-bit controller core using version 1.2 of the open-source Eclipse based LatticeMico™ System.
  • Lattice Diamond 1.2 adds the support for all the ultra-high I/O count MachXO2™ devices, and the wafer level packages needed for very high volume cost sensitive applications.
  • Lattice Diamond 1.2 software now includes updated power, timing and SSO analysis values based on the actual silicon characterization for the LCMXO2-1200 and LCMXO2-1200U devices of the MachXO2 PLD family.
  • Reveal hardware debugger has been validated with the actual silicon of these MachXO2 devices.
  • With Lattice Diamond 1.2 release, users can now tailor the flow to auto-create the reports they want to read after each process sub-step.
  • Power Calculator has been enhanced so it generates the Activity Factor from the VCD file and handles internal signals, not just top-level ports. The VCD file needs to be gate level and matching with the design.
  • ECO Editor now supports User Flash Memory (UFM) initialization for MachXO2-640 and higher density devices.
  • The EBR and distributed memory initialization feature was also enhanced to include the Update Initial Memory dialog box for specifying the initialization settings.
  • To simplify the user interface and avoid confusion, I/O SSO (simultaneous switching output) Analysis was removed from the Place & Route stage of the Process view, however is still available through Spreadsheet View and Package View.
  • Logic Block View now opens as a separate view with its own vertical toolbar. One or more Logic Block Views can be opened from components in Floorplan View, Physical View, or NCD View.
  • Predefined Layouts Four predefined layouts are now available from the Window menu for common design tasks: Analyze RTL, Enter Preferences, Manage Project, and Timing Analysis.
  • Reports View now includes “Generate Hierarchy” and “Run BKM Check” reports. These reports make this information easier to find and provide more detail. Previously this information was only available in the Output view.
  • IPexpress™ contains numerous improvements to existing modules.
  • ispVM® System software has been upgraded to version 18.0.
  • Synopsys® Synplify Pro® for Lattice synthesis tool has been updated, with version E-2010.09-SP2, released in December 2010.
  • Lattice Diamond 1.2 release supports Tcl 8.5.

Lattice Diamond 1.1

  • Initial support for MachXO2 device family.
  • Introduction of Lattice Synthesis Engine (LSE) supporting MachXO2 and MachXO devices families. LSE is the result of several years of development initially focused on Lattice's internal FPGA architecture development. LSE supports both Verilog and VHDL languages and uses SDC format for constraints. It is integrated into the Lattice Diamond design software as a synthesis tool choice when a supported device family is selected.
  • Performance improvements on large designs resulting in up to 20% faster FMax results.
  • LatticeECP3 family final data is included in this software release for timing, power, and SSO noise.
  • Strategy options have been added for LSE support and Update Compile Point Timing.
  • Floorplan View includes a new “Display Congestion” command that has been added which shows a representation of the amount of routing congestion for a PLC component or site.
  • Power Calculator includes new features that have been added for the MachXO2 low power architecture, including Power Option Controller and an EFB page for the embedded function block.
  • Spreadsheet View Spreadsheet View includes enhancements for the BLOCK preference.
  • Source Editor now provides SDC templates for use with VHDL and Verilog HDL files editing.
  • Timing Analysis View has significant performance improvements for recalculating both path delays and changing default speed grade settings.
  • IPexpress™ contains numerous improvements to existing modules and also includes new modules specifically for MachXO2.
  • ispVM® System software has been upgraded to version 17.9.
  • Synopsys® Synplify Pro® for Lattice synthesis tool has been updated, including improved targeting of behavioral HDL to ECP3 sysDSP block cascade feature resulting in higher performance filters.
  • Aldec® Active-HDL™ Lattice Edition simulator has been updated.

Lattice Diamond 1.0

New software introduction. New feature introductions in the following areas greatly increase the software functionality and ease of use over previous software design environments.

  • Design Exploration
    • Design projects in Diamond offer an order of magnitude increased functionality by allowing more robust projects and capabilities that allow design exploration. Key improvements to Diamond projects include the following.
      • Allow the mixing of Verilog, VHDL, EDIF, and schematic sources
      • Implementations, allow multiple versions of a design within a single project
      • Strategies allow implementation “recipes” to be applied to any implementation within a project or shared between projects
      • Manage and choose files for constraints, timing analysis, power calculation, and hardware debug
    • Use Run Manager view to allow parallel processing of multiple implementations in order to explore design alternatives for the best results.
    • Save time by analyzing your design prior to synthesis with the new integrated HDL code checking capability.
  • Ease of Use Throughout
    • The Diamond user interface combines leading edge features and customization while offering better ease of use. All the tools in Diamond now open in “Views” integrated into a common Diamond user interface and have the ability to be detached in separate windows. Once the operation for a single tool view is learned, this knowledge can be applied to other views. New features like the Start Page and Reports view allow easy access to information.
    • ECO Editor provides quick access to commonly used netlist editing functions such as sysIO settings, PLL parameters, and memory initialization. Programmer allows fast reprogramming of FPGAs once the hardware configuration has been setup with ispVM. Getting the job done more quickly is the goal of these tools
  • More Efficient Design Flow
    • The new Timing Analysis view offers an easy to use graphical environment for navigating timing information. A key new benefit in Timing Analysis view is rapidly updated analysis when timing constraints are changed. No longer must you re-implement your design to re-run a TRACE report.
    • Diamond provides easy export of designs to simulators through the new Simulation Wizard.
    • Diamond software adds new capabilities for scripting the design flow. Diamond specific TCL command dictionaries are available for projects, netlists, HDL code checking, power calculation, and hardware debug insertion and analysis.