Diamond Overview

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Overview

Exploring Design Alternatives Made Easy

Finding the best solutions for smaller FPGAs often requires evaluating multiple alternatives. Lattice Diamond allows easy exploration of alternate solutions without resorting to workarounds like multiple projects or different revisions. Diamond provides several unique features that make exploring design alternatives easy:

  • Supports VHDL, Verilog, EDIF, schematics and multiple implementations. One Lattice Diamond project does the work that normally requires multiple projects in other tools.
  • Strategies contain all the tool settings used within an implementation. These are the "recipes" needed to complete your design, and they can be saved and shared easily.
  • Add, change, or remove entire sets of constraints, power voltages, or debug access easily with a mouse click.
  • Utilize Synopsys Synplify Pro or Lattice Synthesis Engine (LSE) to explore additional implementation options for achieving the best results.
  • Run Manager lets you execute implementations in parallel on your multi-core machines to find the best solution faster.

Easy to Use in Many Ways

Adapting to a new tool is hard. No matter how you like to work, Lattice Diamond can adapt to your style. And Lattice Diamond provides tools that make common tasks easier.

  • You can detach tool views to allow you to concentrate on a single tool at time for small monitors or have multiple tool views open if you have multiple monitors.
  • Specific tools have been designed to make common tasks easier. ECO Editor, Programmer, and Reveal are just some examples of tools tailored for making individual tasks easier.

Design Flow Tailored for Lattice Devices

Applications that use low-density and ultra low-density FPGAs require flexibility, verification, and the ability to iterate quickly. Lattice Diamond does this and more.

  • Timing Analysis view saves time by allowing interactive changes to constraints and viewing results without disturbing your design.
  • Simulation Wizard provides easy integration with simulation, even if you aren't a simulation expert.
  • Lattice Diamond has an easy to use GUI, but sometimes a script is the fastest way to do a task. Full Tcl scripting support is provided with interactive help features.

Complete Design Environment

Lattice Diamond contains a complete set of tools for implementing your design. It includes tools for the following areas and third-party tools.

  • Design Entry
  • Synthesis
  • Implementation
  • Analysis
  • On-chip Debug Hardware Analysis
  • Simulation
  • Programming
  • Deployment
  • Synopsys Synplify Pro for Lattice Synthesis
  • Aldec Active-HDL Simulation

Lattice Diamond Complete Feature List

Lattice Diamond design software offers leading-edge design and implementation tools optimized for cost sensitive, low-power Lattice FPGA architectures. Lattice Diamond is the next generation replacement for ispLEVER featuring design exploration, ease of use, improved design flow, and numerous additional enhancements. The combination of new and enhanced features allows users to complete designs faster, easier, and with better results than ever before. Lattice Diamond software is a robust and complete software environment from entering the design to programming your Lattice device. It uses proven implementation engine technology developed for six generations of tools. Below is a list of all the major tool areas provided in the Lattice Diamond software:

Project Management

Features Projects

Lattice Diamond Environment

The Lattice Diamond software environment provides a set of functions including the following tools.

  • File List view for project management
  • Process view for controlling implementation of designs
  • Start page which offers quick links to opening projects, recent projects, software updates, on-line help, and Lattice website
  • Report view which offers a centralized location for viewing all design reports and displays reports from multiple implementations.
  • Centralized location for all outputs, warnings, errors, and scripting control
  • Menus, icons, and controls for all integrated tool views

Robust Project Capabilities

Design projects in Lattice Diamond offer an order of magnitude increased functionality by allowing more robust projects and capabilities that allow design exploration. Key improvements to Lattice Diamond projects include the following.

  • Allow the mixing of Verilog, VHDL, EDIF, and schematic sources
  • Through Implementations, allow multiple versions of a design within a single project for easy design exploration
  • Strategies allow implementation “recipes” to be applied to any implementation within a project or shared between projects
  • Manage and choose files for constraints, timing analysis, power calculation, and hardware debug
  • Use Run Manager view to allow parallel processing of multiple implementations in order to explore design alternatives for the best results. Run Manager allows you to selectively choose implementations in your project and compare the results. Resource usage is also included in the table. And, you can also set how many cores to use for multi-core processors to manage the load on your system.

Design Entry

HDL Entry (Text Editor)

Lattice Diamond includes an intuitive HDL text editor that includes keyword highlight support for: VHDL, Verilog HDL, EDIF, and the Lattice Preference Language. You also set your favorite editor as the default.

Schematic Editor

Schematic Editor view helps you visualize programmable logic designs in a graphical format using block diagrams of HDL blocks or gate-level schematics for all device families.

IPexpress

IPexpress view is the interface to the Lattice catalog of functional modules, reference designs, and intellectual property(IP), all optimized for Lattice programmable products. IPexpress helps accelerate the design process by helping you smoothly configure and integrate these functions into your custom design. Lattice IP cores include some of the most popular industry-standard functions such as PCI bus controllers, DDR memory controllers, Ethernet MACs, DSP functions and many more. To learn more about these IP cores, click here.

Features IPexpress

HDL Analysis

Save time by analyzing your design prior to synthesis with the new integrated HDL code checking capability. The Hierarchy view is automatically opened when the project is opened along with the File list and Process view. Post synthesis, the Hierarchy tab is annotated with the resource utilization to give an idea about the elements used per each level of hierarchy. It is also updated post map with physical (slices) elements.


LDC Editor (Constraint editor for LSE)

Users of the Lattice Synthesis Engine (LSE) tool can now create and edit Synopsys Design Compiler (SDC) synthesis constraints in the new Lattice Design Constraints graphical editor. This editor automatically populates design clock, port and net names and provides real time syntax and semantic checks. It generates an SDC file that can be used with LSE.

LDC Editor

Platform Designer

Platform Designer is a new tool that enables you to create and control a complete hardware system using the Platform Manager 2 device or MachXO2 with external analog sense and control (ASC). Platform Designer’s integrated design environment allows you to configure the device, implement the hardware management algorithm, generate the HDL, simulate, assign pins, and finally generate the JEDEC files required to program and configure the device on the circuit board. Platform Designer contains separate editors for configuring global ASC and device settings; current, temperature, and voltage monitors; fan controller and fault logger components; ports and nodes; and logic controls.

Platform Designer

Synthesis

Lattice Synthesis Engine (LSE)

For MachXO2 and MachXO device families the new Lattice Synthesis Engine (LSE) is available for exploring how to achieve the best results. LSE is the result of several years of development initially focused on Lattice's internal FPGA architecture development. LSE supports both Verilog and VHDL languages and uses SDC format for constraints. It is integrated into the Lattice Diamond design software as a synthesis tool choice when a supported device family is selected. More information on LSE is available here.

LSE Diagram

Synopsys Synplify Pro for Lattice

Lattice Diamond includes the industry-leading synthesis solution, Synopsys Synplify Pro for Lattice, with a range of tools and features that help you manage large designs, and extract the very best fit and performance, optimized for Lattice FPGAs. Synplify Pro for Lattice also includes HDL Analyst, which automatically produces an RTL schematic of your design for analysis and cross-probing with RTL source code. Other advanced features include the following.

  • Behavior Extracting Synthesis Technology (BEST) produces globally optimized designs in a fraction of the time required for traditional tools
  • Comprehensive Language Compiler for supporting a wide range of Verilog and VHDL language constructs
  • SCOPE constraints editor for spreadsheet-like entry of design constraints for synthesis, place and route
  • Integrated module generation for high-performing, area-efficient implementation of arithmetic/datapath functions
  • Automatic RAM inferencing for technology independent RTL source code
  • Integrated language-sensitive HDL source code editor with syntax checker
  • Automatic register balancing of pipelined multipliers and ROMs for improved performance
  • Customized mapping software for each FPGA device family ensures optimal implementation in the target device and technology independence
  • HDL Analyst automatically produces an RTL schematic of your design for analysis and cross-probing with RTL source code. Cross-probing is also possible from the timing report (twr) generated by Diamond
  • Mixed Verilog and VHDL support
  • Compile-point support
  • Automatic re-timing (balancing registers across combinatorial logic) for improved performance
  • Automatic gated-clock and generated clock conversion for efficient implementation of RTL written for an ASIC into an FPGA
Synplify Pro

Implementation

Spreadsheet View

Design Planner in ispLEVER incorporated several functions in a separate tool. These functions are now individual views in Lattice Diamond and work seamlessly with the other views. A key component is the Spreadsheet View. This view allows the ability to enter and view design constraints such as pin assignments, clock resource usage, global preferences, timing preferences and more. Spreadsheet View provides cross probing to several other views and works with the File List view for managing multiple constraints files. When migrating to a lower cost device in one of the device families, Spreadsheet View can show the incompatible pins.

Package View

Package View allows easy graphical assignment of signals to pins. Package View also provides a graphical representation of SSO noise analysis to check noise caused by parallel output switching. Package View provides cross probing to several other views including Spreadsheet View, Floorplan View and others. When migrating to a lower cost device in one of the device families, Package View can show the incompatible pins.

Floorplan View, Physical View, Netlist View, NCD View, Device View

Lattice Diamond provides several abstractions for design and device tasks. Floorplan View provides the ability to view and edit placement constraints. Physical View provides a detailed read-only view of the physical routing of paths for more detailed understanding of timing issues. Netlist View provides browsing of design ports, instances, and nets for drag and dropping into other views such as Package View for setting constraints. NCD View provides access to detailed usage information of physical components such as SLICEs, PIOs, IOLOGIC, and other elements. Device View provides the ability to browse device specific resources and cross-probe to other views. Together these views provide access to the information needed to analyze and constrain the design’s implementation.

ECO Editor

ECO Editor provides quick access to commonly used netlist editing functions such as sysIO settings, PLL parameters, and memory initialization without having to use a full editor such as EPIC. Signal Probe capability allows users to easily assign internal signals to external pins for use as test probes.

EPIC

EPIC device editor provides detailed access and editing of the physical implementation of your design. Physical details like route interconnect, physical element programming, and I/O buffer configuration can be examined or directly edited after the PAR process, giving you ultimate control.

Analysis

Timing Analyzer View

The new Timing Analysis View offers an easy to use graphical environment for navigating timing information. Click on a constraint and see the timing paths, detailed paths, and path schematic views instantly. Timing Analysis View also includes the same information for unconstrained paths, speeding up your timing closure flow. Easy visual cues, such as coloring constraints that fail in red, provide instant feedback on your design. A key new benefit in Timing Analysis View is rapidly updated analysis when timing constraints are changed, including clock jitter analysis. No longer must you re-implement your design to re-run a TRACE report. Instead, change a timing constraint, click update in Timing Analysis and your analysis report is directly run.

Timing View

Power Calculator

Power Calculator uses highly accurate data models along with a data driven power model to provide power estimation and calculation results, graphical power displays, and reports. Thermal resistance options can be used to model real world thermal conditions including heatsinks, airflow, and board complexity. The data driven approach of Power Calculator provides very accurate results for both power estimation and calculation giving you high confidence when targeting the specific power budgets of low power design applications. Power Estimation is also available as a standalone application.

On-chip Debug Hardware Analysis

Reveal Inserter

Reveal Inserter uses a signal-centric model that allows easy insertion of embedded logic analyzer debug hardware for real-time analysis. Reveal features the ability to use, multi-event triggering which can be dynamically changed at run-time.

Reveal Analyzer

Reveal Analyzer features the ability to use, multi-event triggering which can be dynamically changed at run-time and an integrated waveform for displaying captured events from the target FPGA. New in Lattice Diamond is a more streamlined Reveal Analyzer module with multiple cursors and rubber banding for measuring events in the waveform display. And, downloading trace data or setting complex trigger configuration is really fast.

Reveal Analyzer

Tcl Scripting Support

Lattice Diamond software adds capabilities for scripting the design flow. In addition to the Tcl console tab in the environment, a separate Tcl console application allows running scripts independently. Lattice Diamond specific Tcl command dictionaries are available for the following areas.

  • Projects management
  • Netlist queries
  • HDL code checking
  • Power calculation
  • On-chip debug insertion
  • On-chip debug analysis

Simulation

Simulation Wizard

Lattice Diamond provides easy export of designs to simulators through the Simulation Wizard, including support for multi-file testbenches. The Simulation Wizard will guide you through all the necessary steps to get your design to a simulator in the format you want it. Simulation Wizard is the easy way to get exactly what you want.

Simulation Wizard

Aldec Active-HDL Lattice Edition II

Lattice Diamond includes the comprehensive and feature-rich simulation environment Active-HDL Lattice Edition II from Aldec. Active-HDL Lattice Edition II features mixed language simulation of VHDL and Verilog, and many advanced verification and debug features such as Language Assistant, Code Execution Tracing, Advanced Breakpoint Management and Memory Viewing. When using Lattice Diamond with the free license, simulation is enabled for Active-HDL Web Edition II which offers many of the same features with less capacity. Aldec Active-HDL Lattice Edition II and Active-HDL Web Edition II are available on Windows platforms only.

Aldec Active-HDL

Programming

Programmer

Fully integrated into Diamond and standalone, Programmer allows easy direct normal programming of single or multiple FPGA devices. Users can also add support for their own SPI Flash devices directly in Programmer, allowing immediate support for these devices.

Deployment tool

Diamond Deployment Tool provides an intuitive wizard approach to create the appropriate device programming file in the format required by your deployment method. It offers functionality such as file conversion, external memory file generation, improved I2C embedded for the MachXO2 family and Slave SPI support for the LatticeECP3 and LatticeXP2 device families. Getting the job done more quickly is the goal of these tools.

Deployment Wizard

Lattice Diamond Key Concepts

Lattice Diamond design software offers leading-edge design and implementation tools optimized for cost sensitive, low-power Lattice FPGA architectures. Lattice Diamond features provide significant improvements and new concepts not found in earlier Lattice design software tools. Primarily among the new features are expanded projects and the new timing analysis flow.

Report View

Improved Projects Enable Design Exploration

Design projects in Lattice Diamond offer an order of magnitude increased functionality by allowing more robust projects and capabilities that allow design exploration. Key improvements to Lattice Diamond projects include the following:

  • Allow the mixing of Verilog, VHDL, EDIF, and schematic sources
  • Through Implementations, allow multiple versions of a design within a single project for easy design exploration
  • Strategies allow implementation “recipes” to be applied to any implementation within a project or shared between projects
  • Manage and choose files for constraints, timing analysis, power calculation, and hardware debug
  • Use Run Manager view to allow parallel processing of multiple implementations in order to explore design alternatives for the best results. Run Manager allows you to selectively choose implementations in your project and compare the results. You can also set how many cores to use for multi-core processors to manage the load on your system.

Implementations

Implementations define the design structural elements for a project. An implementation contains the structure of a design and can be thought of as the source and constraints to create the design. For example, one implementation may use inferred memory and another implementation may use instantiated memory. There can be multiple implementations in a project, but only one implementation can be active at a time and there must be at least one implementation. You can copy an existing implementation by creating a new one and selecting the source of an existing implementation. An Implementation is automatically created whenever you create a new project. Implementations consist of:

  • Input files
  • Constraint files
  • Debug files
  • Script files
  • Analysis files

Strategies

Strategies are all the implementation related tool settings collected in one convenient location. An implementation defines what is in the design, and a strategy defines how that design will be run by the implementation tools (synthesis, translate, map, par, bitgen, etc.). The strategies in a project are automatically shared among all the implementations, and they can be saved and used in multiple projects. The following are key facts to understanding strategies and their role in Lattice Diamond projects.

  • Strategies are basically implementation "recipes".
  • There are four predefined strategies in Lattice Diamond plus customized user strategies.
  • Predefined Strategies cannot be edited, but they can be cloned and then modified and saved as custom user strategies.
  • Custom user strategies can be edited, cloned, set as the active strategy and removed.
  • There can be many strategies in a project, but only one can be active at a time for each implementation and each implementation must have an active strategy.

Timing Analysis Flow

The new Timing Analysis view offers an easy to use graphical environment for navigating timing information. Simply click on a constraint and see the timing paths, detailed paths, or path schematic views. Easy visual cues, such as coloring constraints that fail in red, provide instant feedback on your design. A key new benefit in Timing Analysis view is rapidly updated analysis when timing constraints are changed, including clock jitter analysis. No longer must you re-implement your design to re-run a TRACE report. Instead, change a timing constraint, click update in Timing Analysis and your analysis report is directly run. The new flow for using timing analysis in Diamond is as follows:

  • Open Timing Analyzer View which reads constraints the design in memory
  • Save constraints as TPF file
  • Click preferences icon in Timing Analyzer view to edit constraints only for timing analysis
  • Edit constraints in Spreadsheet View, then click the update icon in Timing Analyzer view
  • Repeat as necessary. When complete, copy changed constraints back to the design in memory by selecting the preferences in Spreadsheet View and choose export TPF to LPF.
Timing View