Lattice Blog

Share:

Solving the Embedded Challenge of Too Many Signals and Interfaces

Solving Embedded Challenges
Posted 11/07/2017 by Joel Coplen

Posted in

Building designs around state of the art microcontrollers and embedded processors brings along a specific challenge: not enough I/Os and interfaces. Today’s embedded systems have more real-time data and control requirements than ever. I/O requirements might include sensors interfacing over I2C and SPI, pulse width modulated (PWM) outputs for motor control, sideband interrupt, reset signals, and more. Odds are your embedded system is unique enough that finding a perfect match in terms of processing resources, I/O and peripherals with an embedded processor is difficult.

Low-density, I/O-intensive FPGAs are a great solution to this challenge. The provided I/Os in these devices support a variety of programmable settings such as open-drain, current drive, signaling standard (LVDS or LVCMOS). System designers can use these settings to implement I2C, MIPI D-PHY, I2S and a variety of other signaling protocols. Combining these programmable I/O settings with advanced functions like Phase Locked Loops (PLLs) and programmable delay elements allows designers to implement double data rate (DDR) protocols and other source-synchronous protocols (like 7:1 LVDS).

Pairing the programmable logic and memory blocks in the FPGA with these I/Os facilitates the implementation of signal aggregation, interface multiplexing, data buffering, and much more. These functions are the next stage in the evolution of the traditional CPLD function of glue logic. The parallel hardware execution in an FPGA gives big benefits in implementing such systems, with predictable latencies possible for all the operations running through the FPGA.

A simple example is a system requiring the control of a large number of status LEDs with color mixing and dimming effects. An RGB LED will typically require at least 3 high-resolution PWM signals to implement these effects. A system with 10 of these LEDs would require 30 dedicated PWM signals, which may stress the available resources on an embedded microcontroller.

A low-density FPGA can be used to implement these PWM blocks, along with a flexible interface (like SPI) to the embedded microcontroller. The system designer can define and implement a flexible set of control registers in the FPGA used to drive pre-defined colors, set dimming effects and more. An FPGA with embedded user flash memory can further improve this application by leveraging the flash memory to store calibration information related to the LED performance, implementing color correction using a simple lookup table.

The perfect family of FPGAs for these applications is the MachXO3. Plenty of flexible programmable I/Os, combined with an optimized amount of logic resources, make the MachXO3 devices an ideal solution to the problem of today’s embedded connectivity challenges. Lattice has extended the MachXO3 family with our MachXO3-9400 devices, providing the most I/O in the industry in the sub-10K LUT range. Adding these devices to your choice of microcontroller or embedded processor will solve the problem of not enough I/O and interfaces, allowing you to focus on the unique requirements of your design.

Share:

Add your comment

 

 

 

Captcha