Instantiating the Evaluation Core

The IP module evaluation package includes a top-level RTL source (Verilog and/or VHDL) that can be used as an instantiation template for the IP core.

Verilog Designs

To instantiate a Verilog module:

  1. Using a text editor, open your top-level design file.

  2. Open the top-level RTL source located in the \source directory of the Evaluation Pack and copy the contents into your top-level design.

  1. Connect the ports to the IP module by replacing the default port names in the I/O section of the instantiation template with the actual port names from your design.

Note: If the top-level RTL source in the package contains any instantiated PLL and/or specific I/O types, those modules must also be instantiated in your top-level design.

  1. Save your top-level design file.

Note: If you want to check the core implementation result for core evaluation purposes, the included top-level RTL source can be used as your top-level design without modification.

VHDL Designs

To instantiate a VHDL module:

  1. Using a text editor, open your top-level design file.

  2. Open the top-level RTL source located in the \source directory of the Evaluation Pack and copy the contents into your top-level design.

  1. Connect the ports to the IP module by replacing the default port names in the I/O section of the instantiation template with the actual port names from your design.

Note: If the top-level RTL source in the package contains any instantiated PLL and/or specific I/O types, those modules must also be instantiated in your top-level design.

  1. Include attribute statements for Synplify or Leonardo Spectrum synthesis by typing one of the following, depending upon the synthesis tool you have chosen:

----------------This is an attribute for Synplify--------------------

attribute syn_black_box: boolean; attribute syn_black_box of <module_component>: component is true;

---------------------------------------------------------------------

 

---------------This is an attribute for Leonardo Spectrum--------------------

attribute noopt: boolean; attribute noopt of <module_component>: component is true;

---------------------------------------------------------------------

  1. Save your top-level design file.

Note: If you want to check the core implementation result for core evaluation purposes, the included top-level RTL source can be used as your top-level design without modification.