Implementing the IP Module Using ispLEVER

This procedure shows you how to implement the IP module using the ispLEVER Project Navigator and read the timing report.

To implement the IP module and generate the timing report:

1. Open ispLEVER and create an EDIF project in a new place & route directory.

2. Select the target device specified in your IP download readme.htm file (same as you used for synthesis).

3. Delete the existing constraint file created when starting a new project.

4. Copy the evaluation database and constraint files from the <download_name>\<device>\<version>\par directory to your place & route directory. These files are specified in your IP download readme.htm file

5. Rename the copied constraint file to the same name as your project. For example, if your project is named "demo.syn," then the constraint file must be named demo.lct or demo.prf.

6. Choose Source > Import and select the EDIF netlist file.

For CPLD Devices

7. Double-click the Timing Report process to open the Timing Report.

8. You are finished with the evaluation tutorial.

For ispXPGA Devices

7. Double-click the Post-Route Timing Report process to open the Timing Report.

8. You are finished with the evaluation tutorial.

For ORCA/FPSC/EC/ECP/XP Devices

7. Choose Tools > Timing Checkpoint Options and set the options as specified in your IP download readme.htm file.

8. Select the Place & Route Design process, right-click to open the Properties dialog box, and then set the properties as specified in your IP download readme.htm file.

9. Double-click the Place & Route Trace Report process to run place and route and to open the Timing Report.

Note: For some ORCA4 ispLeverCOREs, the Cycle Stealing Process may be required to achieve the required timing specification. Check the ispLeverCORE readme file to see if this additional process step is necessary.

Timing Report File

Some cores are overconstrained to achieve maximum timing performance.  The user may observe timing violations when viewing the timing report.  To obtain actual results, use the Post Route Trace preference files to generate the correct timing report.

1. Replace the preference file (.lct or .prf) in the project directory with the following Post Route Trace file.  Rename the Post Route Trace preference file to match the project name.

• post_route_trace_synplify.lct or .prf for Synplify

• post_route_trace_leonardo.lct or .prf for LeonardoSpectrum

2. From the GUI of the Project Navigator, right-click on Post_Route_Timing_Report (for XPGA) or Place_Route_Trace_Report (for ORCA/ORCA FPSC/EC/ECP/XP).  The new timing file is generated.