                   Memory Stick PRO Host Interface Reference Design                          
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File List (10 files)
 1. RD1109/doc/RD1109.pdf            	                  	--> Memory Stick PRO Host Interface Reference Design document
    RD1109/doc/rd1109_readme.txt                        	--> Read me file (this file)    

 2. RD1109/project/MS_PRO.lpf                              	--> preference file for the design
    
 3. RD1109/simulation/verilog/rtl_verilog.do		        --> verilog rtl simulation script 
    RD1109/simulation/verilog/timing_verilog.do		      	--> verilog timing simulation script 

 4. RD1109/source/verilog/MS_PRO.v							--> source file - top level
    RD1109/source/verilog/FIFO.v							--> source file  
    RD1109/source/verilog/crc_generator.v               	--> source file     
    RD1109/source/verilog/crc_top.v                     	--> source file   
    
 5. RD1109/testbench/verilog/MS_PRO_TB.v              		--> top testbench for simulation 
    
    
                                                                                                                                                                                                                  
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!!IMPORTANT NOTES:!!
1. Unzip the RD1109_revyy.y.zip file using the existing folder names, where yy.y is the current
   version of the zip file
2. If there is lpf file or lci file available for the reference design:
	2.1 copy the content of the provided lpf file to the <project_name>.lpf file under your ispLEVER project, 
	2.2 use Constraint Files >> Add >> Exiting File to import the lpf to Diamond project and set it to be active,
	2.3 copy the content of the provided lct file to the <project_name>.lct under your cpld project.  
4. If there is sty file (strategy file for Diamond) available for the design, go to File List tab on the left 
   side of the GUI. Right click on Strategies >> Add >> Existing File. Then right click on the imported file 
   name and select "Set as Active Strategy".

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Using ispLEVER 
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HOW TO CREATE A ISPLEVER PROJECT:
1. Bring up ISPLEVER software, in the GUI, select File >> New Project
2. In the New Project popup, select the Project location, provide a Project name, select Design Entry Type 
   and click Next.
3. Use RD1109.pdf to see which device /speedgrade should be selected to achieve the desired timing result
4. Add the necessary source files from the RD1109/source directory, click Next
5. Click Finish. Now the project is successfully created. 
6. Make sure the provided lpf or lct is used in the current directory. 

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HOW TO RUN SIMULATION FROM ISPLEVER PROJECT:
1. Import the top-level testbench into the project as test fixture and associate with the device
	1.1 Import the rest as Testbench Dependency File by highligh and right click on the test bench file
2. In the Project Navigator, highlight the testbench file on the left-side panel, user will see 3 
   simulation options on the right panel.
3. For functional simulation, double click on Verilog (or VHDL) Functional Simulation with Aldec 
   Active-HDL. Aldec simulator will be brought up, click yes to overwrite the existing file. The 
   simulator will initialize and run for 1ms.
4. Type "run 1ms" for vhdl and for verilog in the Console panel.A script similar to this will be in the Console panel: 

# KERNEL:                  209  Prescale Register Programmed with 8 
# KERNEL:                  322  Command Register Programmed with 8 
# KERNEL:                  547  TLEN Register Programmed with 30 
# KERNEL:                 3931  FIFO Loaded 
# KERNEL:                 4082  Read status register 
# KERNEL:                 4194  Control Register Programmed with 1B 
# KERNEL:                 4194  Start data transfer to MSPRO 
# KERNEL:               122463  Interrupt occured 
# KERNEL:               122597  Status register checked for 02 
# KERNEL:               123048  start read operation from MS PRO 
# KERNEL:               241789 Data Received = 00 Data Expected = 00 Data Matched
# KERNEL:               241939 Data Received = 01 Data Expected = 01 Data Matched
# KERNEL:               242090 Data Received = 02 Data Expected = 02 Data Matched
# KERNEL:               242240 Data Received = 03 Data Expected = 03 Data Matched
# KERNEL:               242390 Data Received = 04 Data Expected = 04 Data Matched
# KERNEL:               242541 Data Received = 05 Data Expected = 05 Data Matched
# KERNEL:               242691 Data Received = 06 Data Expected = 06 Data Matched
# KERNEL:               242842 Data Received = 07 Data Expected = 07 Data Matched
# KERNEL:               242992 Data Received = 08 Data Expected = 08 Data Matched
# KERNEL:               243142 Data Received = 09 Data Expected = 09 Data Matched
# KERNEL:               243293 Data Received = 0a Data Expected = 0a Data Matched
# KERNEL:               243443 Data Received = 0b Data Expected = 0b Data Matched
# KERNEL:               243594 Data Received = 0c Data Expected = 0c Data Matched
# KERNEL:               243744 Data Received = 0d Data Expected = 0d Data Matched
# KERNEL:               243894 Data Received = 0e Data Expected = 0e Data Matched
# KERNEL:               244045 Data Received = 0f Data Expected = 0f Data Matched
# KERNEL:               244195 Data Received = 10 Data Expected = 10 Data Matched
# KERNEL:               244346 Data Received = 11 Data Expected = 11 Data Matched
# KERNEL:               244496 Data Received = 12 Data Expected = 12 Data Matched
# KERNEL:               244646 Data Received = 13 Data Expected = 13 Data Matched
# KERNEL:               244797 Data Received = 14 Data Expected = 14 Data Matched
# KERNEL:               244947 Data Received = 15 Data Expected = 15 Data Matched
# KERNEL:               245098 Data Received = 16 Data Expected = 16 Data Matched
# KERNEL:               245248 Data Received = 17 Data Expected = 17 Data Matched
# KERNEL:               245398 Data Received = 18 Data Expected = 18 Data Matched
# KERNEL:               245549 Data Received = 19 Data Expected = 19 Data Matched
# KERNEL:               245699 Data Received = 1a Data Expected = 1a Data Matched
# KERNEL:               245850 Data Received = 1b Data Expected = 1b Data Matched
# KERNEL:               246000 Data Received = 1c Data Expected = 1c Data Matched
# KERNEL:               246150 Data Received = 1d Data Expected = 1d Data Matched
	
5. For timing simulation, double click on Verilog (or VHDL) Post-Route Timing Simulation with Aldec 
   Active-HDL. Similar message will be shown in the console panel of the Aldec Active-HDL simulator.
   5.1 Run 1ms to see the complete simulation
   5.2 In timing simulation you may see some warnings about narrow widths or vital glitches. These 
       warnings can be ignored. 
  
   
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Using Diamond Software
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HOW TO CREATE A PROJECT IN DIAMOND:
1. Launch Diamond software, in the GUI, select File >> New Project, click Next
2. In the New Project popup, select the Project location and provide a Project name and implementation 
   name, click Next.
3. Add the necessary source files from the RD1109/source directory, click Next
4. Select the desired part and speedgrade. You may use RD1109.pdf to see which device and speedgrade 
   can be selected to achieve the published timing result 
5. Click Finish. Now the project is successfully created. 
6. MAKE SURE the provided lpf and/or sty files are used in the current directory. 
      
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HOW TO RUN SIMULATION UNDER DIAMOND:
1. Bring up the Simulation Wizard under the Tools menu 
2. Next provide a name for simulation project, and select RTL or post-route simulation
	2.1 For post-route simulation, must export verilog or vhdl simulation file after Place and Route
3. Next add the test bench files form the RD1109/TestBench directory 
	3.1 For VHDL, make sure the top-level test bench is last to be added
4. Next click Finish, this will bring up the Aldec simulator automatically
5. In Aldec environment, you can manually activate the simulation or you can use a script
	5.1 Use the provided script in the RD1109/Simulation/<language> directory
	  a. For functional simulation, change the library name to the device family
	  	i) MachXO2: ovi_machxo2 for verilog, machxo2 for vhdl
	  	ii) MachXO: ovi_machxo for verilog, machxo for vhdl
		b. For POST-ROUTE simulation, open the script and change the following:
			i) The sdf file name and the path pointing to your sdf file.
		   The path usually looks like "./<implementation_name>/<sdf_file_name>.sdf"
		  ii) Change the library name using the library name described above
		c. Click Tools > Execute Macro and select the xxx.do file to run the simulation
		d. This will run the simulation until finish
	5.2 Manually activate the simulation
		a. Click Simulation > Initialize Simulation
		b. Click File > New > Waveform, this will bring up the Waveform panel
		c. Click on the top-level testbench, drag all the signals into the Waveform panel
		d. At the Console panel, type "run 1ms" for VHDL simulation and for Verilog 
		   simulation
		e. For timing simulation, you must manually add 
		   -sdfmax MS_PRO_UUT="./MS_PRO/MS_PRO_MS_PRO_vo.sdf"
		   into the asim or vsim command. Use the command in timing_xxx.do as an example
6. The simulation result will be similar to the one described in ispLEVER simulation section. 
