DDR and I/O Design Resources

 The following information is a summary of available resources to help you with all aspects of implementing DDR (1/2/3/etc.) and I/O design for Lattice programmable products.

Documents

The following documents are available on the Lattice website.

FAQs

The following FAQs are some of the more popular items pertaining to DDR3 and I/O Design.

• How can I terminate a DDR2 or DDR3 memory interface to VTT in LatticeECP3?
• Can I evaluate a Lattice DDR IP core on a Lattice evaluation board without an IP license?
• Why do I need to have external VTT termination only on the DDR2/3 data signals at the Lattice FPGA side but not for the address, command and control signals?
• When running my LatticeECP3 DDR design through software PAR, it fails with a "netsanity check" error like:
  "ERROR - par: netsanitycheck: the clock buf_clk on comp Inst4_DLLDELB port CLKI is driven by general routing through comp clk. Please use the appropriate constraints when using general routing for clocks
• The IBIS model file is text, how can I view the output IO waveform?
• What are the available options for LVDS IO in the LatticeECP3?
• What should I do with the LatticeECP3 DDR3 memory interface VTT termination?
• How can I simulate open drain IO/s?
• How do I implement differential SSTL pads in software for my DDR memory interface design?
• How do I implement edge clock routing from a Primary IO (PIO) in a LatticeECP2/M device?

On the Lattice Website 

Visit the following pages to learn more about various Lattice topics, products, demos, features and more.

• LatticeECP3 IO Protocol Board DDR3 Demo
  • DDR3 Demo Page
  • LatticeECP3 DDR3 Demo Source Code v1.3
  • UG38 LatticeECP3 DDR3 Demo for the LatticeECP3 I/O Protocol Board User's Guide 01.3
• LatticeECP3 Versa Board DDR3 Demo
  • LatticeECP3 Versa Development Kit
  • LatticeECP3 Versa - DDR3 Demo - Design Files for Windows 01.1
  • UG45 DDR3 Demo for the LatticeECP3 Versa Evaluation Board User's Guide 01.0 

Lattice DDR Memory Controller IP Cores

• DDR3
  • DDR3 SDRAM Controller
  • IPUG80 - Double Data Rate (DDR3) SDRAM Controller IP Core User's Guide
  • DDR3 PHY
• DDR2
  • DDR2 SDRAM Controller - Pipelined
  • IPUG35 - DDR/DDR2 SDRAM Controller - Pipelined User's Guide
  • IPUG93 - DDR/DDR2 SDRAM Controller- Pipelined (MachXO2) IP Core User's Guide
• DDR
  • DDR SDRAM Controller - Pipelined
  • IPUG35 - DDR/DDR2 SDRAM Controller - Pipelined User's Guide
  • IPUG93 - DDR/DDR2 SDRAM Controller- Pipelined (MachXO2) IP Core User's Guide
• LPDDR
  • LPDDR SDRAM Controller
  • IPUG92 - LPDDR SDRAM Controller IP Core User's Guide

Lattice Evaluation Boards and Development Kits with DDR memory interfaces

• DDR3
  • LatticeECP3 I/O Protocol Board - UDIMM, 64-bit
  • LatticeECP3 Versa Development Kit - 16-bit
• DDR2
  • LatticeXP2 Advanced Evaluation Board - SODIMM, 32-bit
  • LatticeECP3 PCI Express Development Kit - 16-bit
  • LatticeECP2M PCI Express Development Kit - 16-bit
  • LatticeECP3 AMC Evaluation Board - 32-bit
  • LatticeECP3 Serial Protocol Board - 32-bit
  • LatticeECP3 Video Protocol Board - 32-bit
  • LatticeECP2M SMPTE SDI Evaluation Board - 32-bit
  • LatticeECP2M PCI Express x4 Evaluation Board - 16-bit
  • LatticeECP2M SERDES Evaluation Board - 16-bit
  • LatticeECP2 Advanced Evaluation Board - SODIMM, 64-bit
  • LatticeECP3 HDR-60 Video Camera Development Kit - 16-bit
• DDR1
  • LatticeMico32/DSP Development Board for LatticeECP2 - SODIMM, 32-bit
  • LatticeMico32/DSP Development Board - SODIMM, 32-bit
  • LatticeEC Advanced Evaluation Board - SODIMM, 16-bit
  • LatticeXP Advanced Evaluation Board - SODIMM, 16-bit
• LPDDR
  • MachXO2 Control Development Kit - 16-bit

Outside Lattice

Here are some links & resources you might find useful, relating to DDR & I/O design.

• JEDEC Main Memory Update
• JEDEC Mobile Memory Update
• Micron DRAM Products
• Micron DRAM Module Products
• DDR2 PCB Layout Guidelines (General)
• DDR3 PCB Layout Guidelines (General)