The event was originally broadcast on:
Date: Wednesday, December 13, 2006
Time: 11:00 AM Pacific / 2:00 PM Eastern
Duration: 1 hour
Overview
Static Timing Analysis (STA) is an important step in analyzing the performance of a design. Lattice's ispLEVER STA tools support both pre- and post-layout STA and constraints setting. STA is much faster than timing-driven gate-level simulation and does not require stimulus vector generation. Unlike dynamic analysis, the quality of the static approach is independent of the quality of stimulus vectors. This webcast covers concepts and techniques of STA and practical examples including sample reports, describing timing exceptions, multicycle paths, and hold-time analysis.
Drawing
- One participant who attends the live broadcast and fills out the feedback form will receive an ispLEVER Development Tool for Lattice FPGA and CPLD design. Official Rules.
Speaker Information
 Troy Scott |
Troy Scott
Product Marketing Engineer II
Lattice Semiconductor
Troy Scott is a marketing specialist at Lattice Semiconductor Corporation. He has more than 10 years experience in the EDA and semiconductor industry. Troy's background includes HDL synthesis and simulation, hardware emulation, and IP evaluation and marketing. Troy holds a BSCE from Oregon Institute of Technology and a Graduate Certificate in Computer Architecture and Design from Portland State University.
|
|
|
|
Sign In
