LatticeSC Extreme Performance FPGAs: General Introduction

The event was originally broadcast on:

Date: Wednesday, March 8
Time: 11 a.m. Pacific / 2 p.m. Eastern
Duration: 1 hour

Overview

Learn how to take your design performance to the extreme with a new class of FPGA, called the LatticeSC (System Chip), that combines industry best serial and parallel I/O capabilities, hard IP and an extreme performance LUT based fabric for a best-in-class high density FPGA.

The new 90nm FPGA family offers:

• Extreme Performance 500MHz FPGA fabric
• 3.8Gbps SERDES and PCS 
• PURESPEED 2Gbps I/Os 
• large, fast block RAM 
• MACO: embedded hard IP