Optimizing Verilog Coding for More Efficient FPGA Synthesis

The event was originally broadcast on:

Date: Wednesday, April 9, 2008
Time: 11:00 AM Pacific / 2:00 PM Eastern
Duration: 1 hour

Overview

FPGA designers who target low-cost systems are attempting to pack as much logic as possible into FPGA devices and at the same time need the best performance possible. In this presentation, Lattice Semiconductor provides practical advice on how to write Verilog code that will produce the most efficient implementation in FPGA devices. It will cover detailed do's and don'ts of synthesis coding styles and illustrate the optimization differences with actual FPGA area and timing results.

Speaker Information

Troy Scott

Troy Scott Lattice Semiconductor Troy Scott is a marketing specialist at Lattice Semiconductor Corporation. He has more than 15 years experience in the EDA and semiconductor industry. Troy's background includes HDL synthesis and simulation, hardware emulation, and IP evaluation and marketing. Troy holds a BSCE from Oregon Institute of Technology and a Graduate Certificate in Computer Architecture and Design from Portland State University.