Low-Cost FPGA Supports Full Rate SPI4.2 Implementation

The event was originally broadcast on:

Date: Wednesday, September 6, 2006
Time: 11:00 AM Pacific / 2:00 PM Eastern
Duration: 1 hour

Overview

SPI-4.2 is a standard interface developed by the OIF for 10Gbps traffic flow between Phy and Link Layer devices. It is standard on many ASSPs and FPGAs are commonly used as bridging devices. Until now, only premium FPGA devices could support the demanding interface requirements posed by SPI-4.2. Now, the LatticeECP2 EConomy Plus FPGA supports full SPI-4.2 rates and is the only low cost FPGA family that can claim this.

Attend this NetSeminar and learn about:

• SPI-4.2 Implementation Agreement
• Configuring this interface for the ECP2 using ispLEVER flow
• ECP2 architecture enabling high speed parallel interfaces

Drawing

• One participant who attends the live broadcast and fills out the feedback form will receive an ispLEVER Development Tool for Lattice programmable logic design. Official Rules.

Speaker Information

Van Macomb Strategic Marketing Lattice Semiconductor Van Macomb works in Strategic Marketing at Lattice Semiconductor Corporation. He has nearly 10 years marketing experience in the PLD industry and holds a BS in Chemical Engineering from the University of Connecticut and an MBA from Carnegie Mellon University.