Low-Cost Alternative to CPLDs and FPGAs - MachXO

The event was originally broadcast on:

Date: Thursday, November 1, 2007
Time: 11:00 AM Pacific / 2:00 PM Eastern
Duration: 1 hour

Overview

Designers often turn to small FPGAs or large CPLDs for many types of glue logic functions, such as bus bridging, interfacing and control. Lattice's non-volatile MachXO family combines the best of CPLDs and FPGAs on a single chip, making it ideal for applications requiring high pin-to-pin speed, low power, on-chip memory, or "instant-on" operation.

Attend this webcast and learn how to design with an alternative programmable logic solution that is:

• Low cost
• High performance
• Low power
• Secure
• Easy

Speaker Information

Bertrand Leigh

Bertrand Leigh Applications Engineering Director Lattice Semiconductor Bertrand is Applications Engineering Director at Lattice Semiconductor Corporation. He has more than 15 years experience in the PLD industry and holds a BSEE degree from Oregon State University.