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The event was originally broadcast on:
Date: Wednesday, February 27, 2008
Time: 11:00 AM Pacific / 2:00 PM Eastern
Duration: 1 hour
Overview
The ADS6000 is a family of high sample rate (up to 125 Mega Samples Per Second) Analog-to-digital converters (ADCs) from Texas Instruments. These ADCs output their digital data serially at speeds greater than 800 Mbps. An FPGA interfacing with this serial bit stream needs to implement deserializer logic operating at the same clock speed. This seminar discusses timing challenges and design details of a deserializer logic implementation within an FPGA fabric and provides the details of a modified implementation that meets all the timings.
Speaker Information
 Shyam Chandra |
Shyam Chandra
Lattice Semiconductor
Shyam Chandra is the Product Marketing Manager for the in-system programmable mixed signal products at Lattice Semiconductor Corp. Prior to joining Lattice, Chandra worked for Vantis and AMD in sales and applications and previously was a telecom design engineer with Indian Telephone Industries. Chandra received his Masters degree in Electrical Engineering from Indian Institute of Technology, Madras. |
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