The event was originally broadcast on:
Date: Wednesday, October 11, 2006
Time: 11:00 AM Pacific / 2:00 PM Eastern
Duration: 1 hour
Overview
To meet higher bandwidth requirements, designers are increasingly turning to FPGAs with SERDES to incorporate serial I/O interfaces into their designs. Until now, FPGAs that included high speed SERDES blocks were relatively high-priced. The new LatticeECP2M family brings SERDES to low-cost FPGAs by adding 4 to 16 channels of 3.125Gbps SERDES to a LUT4-based FPGA fabric. Developed on 90nm CMOS utilizing 300mm wafers, the LatticeECP2M FPGA is ideal for cost-conscious applications such as high volume communications, consumer, automotive, video and industrial equipment.
Attend this NetSeminar and learn how to design with a SERDES-based FPGA solution that is:
- Low cost vs. other SERDES-enabled FPGAs
- High Performance
- Full-featured with DDR2 support and DSP
- Very high RAM capacity
Drawing
- One participant who attends the live broadcast and fills out the feedback form will receive an ispLEVER Development Tool for Lattice FPGA and CPLD design. Official Rules.
Speaker Information
 Bertrand Leigh | Bertrand Leigh
Director, Applications Engineering
Lattice Semiconductor
Bertrand Leigh is Director of Applications Engineering at Lattice Semiconductor Corporation. He has more than 15 years experience in the PLD industry and holds a BSEE degree from Oregon State University. |
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