The event was originally broadcast on:
Date: Wednesday, October 3, 2007
Time: 11:00 AM Pacific / 2:00 PM Eastern
Duration: 1 hour
Overview
FPGA designers have long faced the task of verifying functional correctness of their designs. The new Reveal software included in the ispLEVER 7.0 release is a next generation FPGA on-chip debug tool. The Reveal software has significant advances for usability and advanced features compared to the previous ispTRACY software. This webcast will cover the following areas:
- Lattice design flow for debug using Reveal software
- Explain key benefits including ispLEVER integration
- Explain new advanced triggering architecture
- Demonstration of debug insertion and analysis
Speaker Information
Brian Caslis
Brian Caslis is a senior software product planning engineer at Lattice Semiconductor Corporation. He has over 25 years experience in hardware design, applications, technical marketing, and product marketing. Prior to joining Lattice, Brian has held senior EDA marketing positions at Mentor Graphics, Synopsys, and Synplicity, where he managed the marketing strategy for verification products. Brian has a BSEE degree from Worcester Polytechnic Institute. |
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