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The event will broadcast on:
Date: Wednesday, February 22, 2006
Time: 11:00 AM Pacific / 14:00 PM Eastern
Duration: 1 hour
Presented By
Lattice Semiconductor
Overview
Designers are increasingly turning to FPGAs to help accelerate DSP performance and add extra compute power as a co-processor. Until now, FPGAs that included advanced DSP blocks were fairly expensive. However, Lattice's latest generation of low-cost FPGAs have built-in, advanced DSP blocks that each contain a pipelined multiplier/accumulator engine. This extra DSP processing power can be unleashed by system designers through an easy-to-use suite of design tools developed by Lattice for its new DSP-optimized FPGA family.
Attend the Lattice webcast on February 22 and learn how to implement high-performance DSP functions in the latest FPGAs that deliver low system cost at performance levels higher than possible with previous FPGA families. The new FPGA family, in general, offers:
- Low cost vs. other DSP-enabled FPGAs
- High performance
- Pre-engineered DSP acceleration engines
- Easy-to-use tool suite
The Webcast will be moderated by Dave Bursky, Editor-at-Large for Electronic Design
Drawing
One participant who attends the live broadcast and fills out the feedback form
will receive an ispLEVER Development Tool for Lattice FPGA and CPLD design.
See Official Rules
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