Basics of Interfacing a High Speed ADC to an FPGA

The event was originally broadcast on:

Date: Wednesday, September 26, 2007
Time: 11:00 AM Pacific / 2:00 PM Eastern
Duration: 1 hour

Overview

The LatticeECP2/M and LatticeXP2 FPGAs offer designers a low cost and feature rich platform for interfacing with high speed Analog to Digital Converters (ADCs). Interfacing high speed ADCs can present several challenges to designers including: DDR to SDR Conversion, LVDS Buffers, Tight Timing Margins, and High Data Rates in FPGA. However, the designer can simplify the task by using the built-in features of the LatticeECP2/M and LatticeXP2 FPGA families. Learn about the basics of interfacing a high speed ADC to these Lattice FPGAs and the performance that these Lattice devices can deliver.

Speaker Information

Bertrand Leigh	Bertrand Leigh Applications Engineering Director Lattice Semiconductor Bertrand is Applications Engineering Director at Lattice Semiconductor Corporation. He has more than 15 years experience in the PLD industry and holds a BSEE degree from Oregon State University.
Jeff Davis	Jeff Davis Applications Engineer Lattice Semiconductor Jeff Davis is an Applications Engineer for Lattice Semiconductor Corporation. He holds a MSEE degree from Portland State University and BSME degree from Oregon State University. Prior to joining Lattice, he was an Instrumentation & Controls Engineer for over 10 years.