HILLSBORO, OR - FEBRUARY 22, 2010 - Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced that its LatticeECP3™ FPGA family has been chosen from among hundreds of nominations as a Finalist in the 20th Annual EDN Innovation Awards competition. The Innovation Awards honor the people, products and technologies that have shaped the semiconductor industry over the past year.
"We received an impressive number of nominations for our 2009 Innovation Awards program," said Rick Nelson, EDN editor-in chief. "Over the past several weeks, our editors faced the difficult task of narrowing down an impressive field of contenders and finding the freshest, most inventive, and undeniably outstanding nominations that were worthy of being named Finalists for EDN's 2009 Innovation Awards. In the FPGA category, Lattice's ECP3 FPGA family was one of the outstanding products our editors chose."
The LatticeECP3 family defines a new mid-range, value-based class of FPGAs, not only by further reducing costs, but also by reducing total power consumption by over 50% for typical designs, compared to competitive SERDES-capable FPGAs. For example, to minimize power consumption the LatticeECP3 FPGA family uses variable channel lengths, optimized low-power transistors, and improved routing defaults and algorithms. By making careful design choices and minimizing die size, Lattice can offer designers the benefits of high speed serial I/O and processing capabilities, without the power and cost premiums typically associated with these types of devices. With these features, the LatticeECP3 FPGA family is ideally suited for deployment in high volume cost- and power-sensitive wireless infrastructure and wireline access equipment, as well as video and imaging applications.
"We are honored to be named a Finalist in the EDN Innovation Awards competition, one of our industry's most sought-after honors," said Sean Riley, Corporate Vice President and General Manager of High Density Solutions. "Our ECP3 FPGA family already is among the most honored programmable logic products of 2009, and the large number of design wins we are experiencing is evidence that customers were eager for a new class of mid-range devices."
EDN uses a combination of audience votes, balloting by the EDN Editorial Advisory Board and voting by EDN's editorial staff to determine the ultimate winners. Voting will continue through March 19 at: www.edn.com/survey.asp?layout=survey&survey_id=1490001549. EDN will present the awards April 26 at a ceremony during the Embedded Systems Conference in San Jose, CA.
The low power, high value LatticeECP3 FPGA family is comprised of five devices that offer standards-compliant multi-protocol 3G SERDES, DDR1/2/3 memory interfaces for low cost FPGAs and high performance, cascadable DSP slices that are ideal for high performance RF, baseband and image signal processing. Toggling at 1Gbps, the LatticeECP3 FPGAs also feature the fastest LVDS I/O available in a mid-range FPGA family, as well as embedded memory of up to 6.8 Mbits. Logic density varies from 17K LUTs to 149K LUTs with up to 586 user I/O. The LatticeECP3 FPGA family's high performance features include:
With these features, the LatticeECP3 FPGA family is ideally suited for deployment in high volume cost- and power-sensitive wireless infrastructure and wireline access equipment, as well as video and imaging applications. For more information about the LatticeECP3 FPGA family, visit www.latticesemi.com/products/fpga/ecp3
Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions. For more information, visit www.latticesemi.com
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For more information contact:
Brian Kiernan, Corporate Communications Manager
Lattice Semiconductor Corporation
brian.kiernan@latticesemi.com
voice: (503) 268-8739
fax: (503) 268-8193
© Lattice Semiconductor Corporation 2012
