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Lattice Semiconductor and Mentor Graphics Schedule Joint FPGA Customer EventsHILLSBORO, OR - March 14, 2005 - As part of an expanding strategic partnership, Lattice Semiconductor today announced a series of joint FPGA customer events with Mentor Graphics; these will include a series of regional joint seminars in North America as well as participation by Lattice in Mentor's upcoming EDA Tech Forum and User2User, the Mentor User Group (MUG) conference. At these events, Lattice and Mentor Graphics will demonstrate how the power of their combined silicon and software products maximizes designer productivity and shortens system development time. Through a comprehensive OEM agreement initiated in 1999, Lattice has resold Mentor's synthesis and simulation tools as part of its programmable logic design solution. "Lattice is in the process of launching new FPGA products that will transform the programmable logic landscape," said Chris Fanning, Lattice vice president of software. "Lattice and Mentor Graphics will show the FPGA design community that our combined solutions provide technology and value that are unique." The joint seminars will include Lattice's best in class FPGA device architectures (including its recently announced non-volatile, instant-on LatticeXP" family), ispLEVER Design Tools, and Mentor Graphics FPGA design flow, featuring Precision RTL synthesis and the ModelSim simulator. These 3-hour seminars are initially scheduled for the following cities:
Seminars will also be scheduled for Munich, Shenzhen and Shanghai. Mentor's first 2005 EDA Tech Forum is scheduled for Long Beach, CA on March 16. The EDA Tech Forum offers attendees the opportunity to learn about the latest technology trends and challenges facing the EDA design community. Lattice will participate in the product showcase, featuring its latest Flash- and SRAM-based FPGA families. Lattice will attend the Mentor User Group (MUG) conference April 27-29 in Santa Clara, CA. This conference is unique in that its organization, content and participants are managed and selected solely by the Mentor User Group. Lattice will present a technical paper on its best in class LatticeECP" and LatticeEC" FPGA DDR interface implementation, and will participate in the associated vendor fair. Additional information regarding these events can be found on the Lattice website, www.latticesemi.com. To view a new self-running, narrated demonstration of Lattice's ispLEVER Design Tools, go to the following page and click the "View the ispLEVER Flash Demo" icon: http://www.latticesemi.com/products/devtools/software/index.cfm. About Lattice Semiconductor Lattice Semiconductor Corporation provides the industry's broadest range of Field Programmable Gate Arrays (FPGA) and Programmable Logic Devices (PLD), including Field Programmable System Chips (FPSC), Complex | Programmable Logic Devices (CPLD), Programmable Mixed-Signal Products (ispPAC®) and Programmable Digital Interconnect Devices (ispGDX®). Lattice also offers industry leading SERDES products. Lattice is "Bringing the Best Together" with comprehensive solutions for system design, including an unequaled portfolio of non-volatile programmable devices that deliver instant-on operation, security and "single chip solution" space savings. Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in communications, computing, consumer, industrial and military end markets. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124-6421, USA; telephone 503-268-8000, fax 503-268-8037. For more information about Lattice Semiconductor Corporation, visit http://www.latticesemi.com Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our silicon wafer suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements. # # # Lattice Semiconductor Corporation, Lattice (& design), L (& design), ispGDX, ispLEVER, ispPAC, LatticeEC, LatticeECP, LatticeXP and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries. GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders. For more information contact: Brian Kiernan, Corporate Communications Manager |