 |
||
 New Account
Sign In
|
Lattice Introduces ispClock High-Performance Clock Generator Devices- Revolutionary devices provide unprecedented performance, flexibility in support of high-performance clock network designs on electronic circuit boards - HILLSBORO, OR - June 7, 2004 - Lattice Semiconductor Corporation (NASDAQ: LSCC) today introduced its revolutionary new family of ispClock™ in-system programmable clock generator devices. The first devices in the ispClock5500 family, the 10-output ispClock5510 and 20-output ispClock5520, combine a high- performance clock generator with a flexible, Universal Fan-out Buffer. The on-chip clock generator can provide up to 5 clock frequencies ranging from 10MHz to 320MHz using a high-performance PLL and clock multiply and divide facilities. The Universal Fan-out Buffer can drive up to 20 clock nets using either single-ended or differential signaling, with individual output control for improved signal and timing integrity. The new devices provide an unprecedented level of performance and flexibility in support of high-performance clock network designs on electronic circuit boards. The new product family marks the first application of Lattice's programmable mixed signal technology to the clock integrated circuit market, estimated at $1 billion and projected to grow at a 20% annual rate over the next four years. First Single-Chip Solution for Entire Clock Tree Design "Lattice is extending the benefits of integration, in-system programmability and superior performance to clock management," said Stan Kopec, vice president of corporate marketing at Lattice Semiconductor. "Historically, clock networks were designed using multiple devices with limited functionality at various levels of the clock hierarchy. The new ispClock devices are the first products that conveniently and accurately solve the entire clock tree design problem with a single chip." A Comprehensive Improvement Over Traditional Clock Network Design In contrast, ispClock5500 devices compensate for timing errors due to different trace length clock nets through a programmable skew feature, match trace impedances with output impedances by programming each output characteristic, and reduce EMI by programming output switching speed or slew rate. This results in board space savings, improved signal integrity, a simpler clock net hierarchy, improved timing convergence and lower cost. The ispClock5500 devices' ability to store up to four timing and output configurations and easily switch between them further extends their utility by supporting easy clock margining (operating a circuit board at higher than typical frequency to evaluate design robustness) and power management (conserving dynamic power consumption by "downshifting" to a more efficient, lower frequency when performance is less critical). In-system programmability via the on-chip boundary scan port helps debug complex timing problems and tune individual network timing for best performance. PAC-Designer Software Pricing and Availability About Lattice Semiconductor Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communications, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124-6421, USA; telephone 503-268-8000, fax 503-268-8037. For more information about Lattice Semiconductor Corporation, visit http://www.latticesemi.com Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, estimates of market size and growth rate, our dependencies on our silicon wafer suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements. # # #
Lattice Semiconductor Corporation, Lattice (& design), L (& design), GDX, ISP, ispClock, PAC, PAC-Designer and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries. GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders. For more information contact: Brian Kiernan, Corporate Communications Manager |