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Lattice Delivers ispLEVER v3.1 Design Tools- Enhanced Design Tools Ease Design Tasks and Improve Performance - HILLSBORO, OR - November 17, 2003 - Lattice Semiconductor Corporation (NASDAQ:LSCC), producer of the world's broadest programmable logic offering, today announced the release of ispLEVER version 3.1, the latest enhanced design tool suite for In-System Programmable FPGA, CPLD, and ispGDX� device design. The ispLEVER software supports design with the entire array of Lattice digital programmable logic devices with a single, familiar user interface. The software includes tools for design entry, HDL synthesis, verification, device fitting, place & route, and programming - everything needed to complete a design project in an efficient package. Lattice has partnered with CAE leaders Synplicity and Mentor Graphics to ensure the industry's best HDL synthesis and simulation tools are included as part of every ispLEVER package. ispLEVER v3.1 includes new features and enhancements to allow users to take full advantage of the complete range of Lattice's innovative device architectures. "We continue to enhance the ispLEVER tools with each release," stated Stan Kopec, Lattice vice president of marketing. "A key to our success has been to provide our customers a simple, yet powerful interface they can quickly master. With improvements to nearly every aspect of the design tools suite, the ispLEVER v3.1 software release builds on that tradition." "An important goal of our software development methodology is to ensure our users enjoy consistent results and smooth operation," said Chris Fanning, Lattice vice president of software. "Our methodology, coupled with innovation and hard work, has enabled us to release the most robust and user friendly design tool in our company's history." New Features Designers can now edit many project source files while a design process is running. This improves productivity by reducing downtime experienced while waiting for complex operations to be completed. The Lattice IP/Module Manager has been expanded to support Lattice ispXPLD™ products. IP cores supporting this innovative architecture are in development and will be available soon. A new preference editor Graphical User Interface (GUI) for ORCA� FPGA devices simplifies the design flow for the ORCA FPGA families, providing a single facility in which the user may enter and edit design constraints critical to achieving design function, performance, and the highest device utilization. Productivity Enhancers Lattice's Revision Control system is designed to help designers more easily organize complex design decision trees. This greatly enhances the iterative processes of refining performance and design debugging. In addition, the Revision Control system has been upgraded to support CPLD and ispGDX device design. The constraint/preference editor now includes improved constraint reporting and allows the user to perform complex sorting operations, making it easier to manage and complete hundreds of signals, commonplace in today's digital design world. Lattice's design entry interface has been enhanced to provide nodal (internal signal points) constraints (directing the signal path through the complex device architecture) and new global constraints to give greater control over automatic buffer insertion and clock enable optimization. Enhancements have also been made to Lattice's innovative HTML-formatted, hyperlinked reporting system to help designers easily understand and trace the signal paths that have been implemented in their target architecture. The new FPGA Floorplanner is more versatile and easier to use. One integrated GUI is now available to edit either pre- or post-map FPGA floor plans and assign blocks of logic to specific logic elements or physical pins. This is critical to high-speed system design because it allows users to place interacting components in close proximity, thus assuring the highest possible design performance. Lattice's ispLEVER development tools are designed to extract the highest performance and utilization from the industry's most diverse and powerful portfolio of In-System Programmable logic devices, including the ispXPGA™, ORCA, ispXPLD, ispMACH™, ispLSI�, ispGDX, and ispGAL� product families. The ispLEVER development tools are available for PC (Windows NT, 2000, XP) and Unix (Solaris 2.8) operating systems. About Lattice Semiconductor Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communication, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124 USA; Telephone 503-268-8000, FAX 503-268-8037. For more information on Lattice Semiconductor Corporation, access our World Wide Web site at http://www.latticesemi.com. Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our silicon wafer suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements. # # #
Lattice Semiconductor Corporation, Lattice (& design), L (& design), in-system programmable, ispXPGA, ispXPLD, ORCA, ispMACH, ispGDX, ispLEVER, ispLSI, ispGAL and ISP are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries. GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders. For more information contact: Tim Schnettler, Design Tools Marketing Manager |