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Lattice Demonstrates Robust Interoperability at University of New Hampshire XAUI PlugfestHILLSBORO, OR - AUGUST 7, 2003 - Lattice Semiconductor (NASDAQ:LSCC) today announced successful interoperability of its ORT82G5 Field Programmable System Chip (FPSC) with a variety of devices from other vendors. The tests were conducted at the recent XAUI PlugFest at the InterOperability Laboratory (IOL) of the University of New Hampshire's Research Computing Center. The ORT82G5 is the industry�s fastest programmable backplane transceiver, with 8 channels of SERDES each operating at up to 3.7Gbits/sec. It is targeted at XAUI- and Fibre Channel-based backplane applications. With industry- leading data rates, low jitter, low power and hundreds of thousands of programmable gates, the ORT82G5 backplane transceiver meets the high-performance and high-reliability demands of carrier-class 10 Gigabit Ethernet communications systems. "Lattice is committed to UNH InterOperability Laboratory testing as it gives us a chance to demonstrate to customers the robustness and superior performance of our SERDES technology when compared to competitors and partners alike," commented Stan Kopec, vice president of marketing at Lattice Semiconductor. "The ORT82G5 is production-proven and has been deployed in a variety of customer systems. From that standpoint, this exercise is analogous to a major league baseball all-star attending a tryout - he�s already demonstrated his ability, but is always ready to show what he�s got. We invite anyone to hook up to our transceivers: seeing is believing. If a device meets the XAUI standard, then the ORT82G5 will interoperate with it," added Kopec. Test Configuration and Results "The Lattice ORT82G5 solution performed very well in XAUI interoperability tests with a variety of vendors," said Bob Noseworthy, 10 Gigabit Ethernet Consortium Manager at UNH IOL. "The Lattice testing is a great example of the value of the IOL, providing a non-partisan venue for the objective evaluation of programmables and ASSPs interoperating. This process demonstrates to potential users the real-world capabilities of a SERDES, unlike published specifications or simulations," Noseworthy added. "As high-speed serial products are introduced into the market, the importance of interoperability testing continues to grow," stated John D'Ambrosia, manager of semiconductor relations for Tyco Electronics. "Lattice and Tyco Electronics share a common belief and commitment to demonstrate the practical interoperability of our products." For customer-specific interoperability testing, Lattice has introduced its High-Speed SERDES Briefcase Evaluation Board, an interoperability and evaluation system for Lattice�s portfolio of high-speed backplane transceivers. The board comes equipped with a socketed ORT82G5 or ORSO82G5 FPSC, along with Lattice�s ispPAC� Power1208 in-system programmable (ISP™) Power Manager device and ispGDX2™-256 high-speed crosspoint switch device providing 16 full-duplex SERDES channels. The Evaluation Board includes on-board power supplies to support regulated 3.3V, 2.5V, 1.8V and 1.5V busses. The Power1208 provides complete power sequencing, monitoring and management. The board also features 24- and 40- inch FR-4 traces and an on-board 156MHz oscillator. Ample connectors are available to examine ORT82G5, ORSO82G5 or ispGDX2 SERDES outputs. The Board also comes with Lattice�s ORCAstra™ software tool which provides a convenient user interface to manage the real-time configuration of ORT82G5 and ORSO82G5 operational modes during evaluation and debug. About UNH InterOperability Laboratory About Lattice Semiconductor Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communication, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124 USA; Telephone 503-268-8000, FAX 503-268-8037. For more information on Lattice Semiconductor Corporation, access our World Wide Web site at http://www.latticesemi.com. Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward- looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our silicon wafer suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company�s Securities and Exchange Commission filings. Actual results may differ materially from forward- looking statements. # # #
Lattice Semiconductor Corporation, Lattice (& design), L (& design), in-system programmable, ISP, ispGDX2, ispPAC, ORCAstra, sysHSI, and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries. GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders. For more information contact: Sean Hildenbrand, Public Relations |
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