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Lattice Launches 3rd Generation ispLEVER Design Tools- Comprehensive, Integrated Tools Support All Lattice In-System Programmable™ Logic Devices; New Features Further Enhance Industry Leading CAE Tools - HILLSBORO, OR � February 24, 2003 - Lattice Semiconductor Corporation (NASDAQ: LSCC), the leading supplier of integrated programmable logic and SERDES solutions, today announced the release of ispLEVER version 3.0, a powerful new generation of its ispLEVER design tool suite. Lattice's ispLEVER development tools are designed to extract the highest performance and utilization from the industry's broadest and most powerful portfolio of programmable logic devices, including Lattice's ispXPGA™ and ORCA� FPGAs, ispXPLD™ and ispMACH™ CPLDs, ispGDX� programmable interface devices and ispGAL� SPLD product families. With this release, Lattice's ispLEVER software continues to build on its reputation as "The Simple Machine for Complex Design™" by providing run-time performance improvements, updated 3rd party tool support, expanded Lattice device support and key functional enhancements. "In the past year, we've made significant improvements to nearly every aspect of our design tools," stated Stan Kopec, Lattice Vice President of Marketing, "The ispLEVER platform has proven to be extremely flexible and efficient, more than able to accommodate new features while retaining a familiar look and feel." The new ispLEVER v3.0 software includes improvements in logic compilation run-time of up to 30% compared with earlier versions, a streamlined installation procedure, new IP and macro support, and further integration of the ORCA FPGA design flow into the ispLEVER suite. Noteworthy enhancements in ispLEVER v3.0 also include an automated Revision Control system. Revision Control helps the designer keep track of multiple design revisions with a simple GUI hierarchical tree. When Revision Control is enabled, every action initiated by the user is tracked and instantly displayed in a Revision Control tree. The user can jump to any point in the tree with one click. Branches of the Revision Control tree can be deleted if desired, and the entire Revision Control system can be toggled on/off at any point in the design process. The ispLEVER v3.0 software supports timing checkpoints in the FPGA design process. Timing checkpoints speed the FPGA design compilation process by automatically checking compilation results while the software is running. If it appears the user-defined constraints will not be met, the user is alerted so the process can be stopped and changes made. This increases the efficiency of the design cycle by reducing time spent compiling designs. Other powerful features and tools in this release include:
Lattice continues to lead all programmable logic suppliers by integrating and supplying industry leading synthesis and simulation tools from Mentor Graphics� and Synplicity�. Lattice supplies Leonardo Spectrum� and Synplify� VHDL and Verilog synthesis tools and the ModelSim� RTL and Timing Simulation tool integrated into a variety of its ispLEVER design solutions. In addition, Lattice provides support for other leading third-party design tools such as Synopsys, Cadence, and others via an efficient EDIF netlist interface. ispLEVER v3.0 includes updates for the latest versions of all these tools. The ispLEVER development tools are available for PC (Windows NT, 2000, XP) and Unix (Solaris 2.8) operating systems. Availability About Lattice Semiconductor Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communication, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124 USA; Telephone 503-268-8000, FAX 503-268-8037. For more information on Lattice Semiconductor Corporation, access our World Wide Web site at hhttp://www.latticesemi.com. Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties, including technological and product development risks, market acceptance and demand for our new products, the impact of competitive products and pricing, and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements. # # #
Lattice Semiconductor Corporation, Lattice (& design), L (& design), in-system programmable, ispXPGA, ispXPLD, ORCA, ispMACH, ispGAL, ispGDX, ispLEVER, ispEXPLORER, Performance Analyst, SpeedSEARCH, ispVM, The Simple Machine for Complex Design and ISP are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries. GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders. For more information contact: Sean Hildenbrand |