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Lattice Announces New In-System Programmable Digital Crosspoint Family with High-Speed SERDES- 850 Mbps Programmable SERDES Plus General Interface Support to 3.0ns / 330MHz - HILLSBORO, OR - OCTOBER 21, 2002 - Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced a new generation of ispGDX� in-system programmable (ISPTM) digital crosspoint devices called the ispGDX2 family that provide customers with cost effective interconnect and interface solutions. The new devices feature from 64 to 256 programmable I/O pins with as many as 16 full-duplex 850 Megabit/sec (Mbps) SERDES channels integrated into a programmable architecture that includes multiplexers, routing, and control logic. Programmable sysI/OTM pins support a variety of advanced I/O standards at speeds of 300MHz or greater, while programmable sysCLOCKTM phase-locked-loops (PLLs) provide precise timing control. All devices will be available in 3.3, 2.5, and 1.8-volt power supply versions. "This new generation of ispGDX devices provides a universal interface capability that supports advanced parallel and serial protocols cost-effectively," stated Stan Kopec, Lattice vice president of corporate marketing. "Our goal for the ispGDX2 family is to give our customers the flexibility and performance to implement exactly the interface functionality they need without compromise or wasted expense." The ispGDX2 devices are suitable for many applications including the implementation of switched backplanes, low-cost serial links, standard translation, bus multiplexing, and the consolidation of drivers, transceivers, and SERDES. The devices provide the flexibility and time-to-market associated with programmability along with the benefits of JTAG testability to these applications. At less than $2.00 per full-duplex SERDES channel, the ispGDX2 family provides the most cost-effective programmable high-speed SERDES in the market. This price per channel is dramatically below that of alternative FPGA solutions that include pre-defined amounts of general-purpose programmable logic and memory that may not be optimal for a particular application. The ispGDX2 approach allows system designers to implement streamlined high bandwidth interfaces independently of general-purpose programmable logic to give the greatest flexibility. Unique Architecture Provides Universal Serial / Parallel Interface Solution The new ispGDX2 architecture has a single-level programmable Global Routing Pool. Dedicated programmable control logic blocks provide control for multiplexing, clocking, register and output enable control functions. Control functions are organized on a nibble (4-bit) basis to give granularity together with silicon efficiency. Real-time signal multiplexing of up to 192 to 1 is available for very fast signal switching and multi-port interface applications. Each ispGDX2 device supports eight I/O banks of eight to thirty-two pins each with individual VCCO pins to control output levels. Each I/O pin can be configured to support high-speed memory interfaces, advanced bus standards, or general-purpose interfaces. General-purpose interface support includes LVTTL or LVCMOS (3.3, 2.5 or 1.8 Volts). Programmable drive levels for these standards facilitate the elimination of series termination resistors, further reducing overall system cost. Interface to high speed DRAMs, SRAMs, and other high performance memory devices is made possible with SSTL2, SSTL3, and HSTL I/O support. The family also supports GTL+ and PCI I/O configurations for use in high-speed bus interfaces. LVDS, Bus LVDS, LVPECL and CTT support is available in support of differential signaling across backplanes and between sub-systems. For the fastest family members, key interface specifications include 3.0ns pin-to-pin logic delays, 2.0ns input set-up times and 3.2ns clock-to-output delays. Pipelined frequencies of 330MHz or greater can be supported. Each device has between 2 and 4 independent sysCLOCK PLLs to manage timing. The programmable PLLs allow clocks to be multiplied and divided, or to be selectively delayed based on the application need while supporting a period jitter of less than 150ps at frequencies of up to 320MHz. The devices are non-volatile and in-system programmable via an IEEE 1149.1 boundary scan port. This feature allows pin-to-pin connectivity and functions to be modified on-board, providing support for generic, reprogrammable backplanes and board interfaces. JTAG-compliant boundary scan test also provides enhanced system testability. Design Tools Design Tools Price and Availability For high-volume applications (25,000 or more pieces) beginning in 2003, pricing for the ispGDX2-256 device in the 484-ball fine pitch BGA package (1mm ball pitch) is projected as low as $29.00 depending on speed grade, temperature range and power supply options. Remaining members of the family, the ispGDX2-64 and ispGDX2-128, are expected to be released to production during the first half of 2003. About Lattice Semiconductor Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communications, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124 USA; Telephone 503-268-8000, FAX 503-268-8037. For more information on Lattice Semiconductor Corporation, access our World Wide Web site at http://www.latticesemi.com. Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our silicon wafer suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company�s Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements. # # # Lattice Semiconductor Corporation, L (& design), Lattice (& design), in-system programmable, ispLEVER, ispGDX, ISP, sysHSI, sysIO, sysCLOCK and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries. GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders. For more information contact: Sean Hildenbrand, Public Relations |