Lattice Releases Second ispMACH 5000VG SuperBIG CPLD

- New Device is 50% Bigger Than Largest Competitive CPLDs

HILLSBORO, OR - JANUARY 7, 2002 - Lattice Semiconductor Corporation today (NASDAQ: LSCC) announced the release of the ispMACH 5768VG, featuring 768 high-performance logic macrocells, the smallest member of the ispMACH 5000VG SuperBIG™ CPLD family. This release continues to expand the 3.3V-ispMACH 5000VG family, which also includes the previously released 1024 macrocell ispMACH 51024VG device. This in-system programmable (ISP™) logic family, which provides up to double the logic capacity of Lattice's popular ispLSI� 5000VE devices, includes new features such as advanced I/O standard (GTL+, HSTL, SSTL, etc.) sysIO™ support and sysCLOCK™ Phase Locked Loops (PLLs). Performance for the ispMACH 5768VG is specified at 5ns pin-to-pin logic delays (tPD) with an operating frequency (fMAX) of 178 MHz, world-class performance for a device of this density. The release of this family represents the completion of Lattice's second generation of BFW (Big-Fast-Wide) products, consisting of the 3.3V ispMACH 5000VG, ispLSI 2000VE and ispLSI 5000VE families.

"The ispMACH 5000VG family delivers CPLD performance and predictability while supporting logic densities and system integration capabilities previously only available in FPGAs," said Steve Stark, Director of Product Marketing at Lattice. "System designers now have a powerful new CPLD family to implement their next generation logic designs."

The devices from the ispMACH 5000VG family incorporate a SuperWIDE™ macrocell architecture pioneered in Lattice's ispLSI 5000V family. Logic capacities beginning at 768 macrocells are large enough to hold multiple functions commonly implemented in CPLDs such as bus bridges, memory controllers, and control logic, and far exceed the 512 macrocell maximum typically found with competitive CPLDs. The large number of sysIO-capable pins (from 196 to 384 per device) provided in the ispMACH 5000VG devices makes them ideal for wide bus interface applications. The instant power-up capability of these devices makes them suitable for power-up sequence control in large, complex systems.

sysIO Capability for Board-Level Performance
Each I/O pin on the ispMACH 5000VG devices can be configured to support high-speed memory interfaces, advanced bus standards, or general-purpose interfaces. General-purpose interface support includes LVTTL or LVCMOS (3.3, 2.5 & 1.8 Volts). The LVTTL and LVCMOS 3.3 interfaces are 5-Volt tolerant, supporting easy integration into legacy designs. Programmable drive levels for these standards facilitate the elimination of series termination resistors, reducing overall system cost.

Interface to high speed DRAMs, SRAMs, and other high performance memory devices is made possible with SSTL2, SSTL3, and HSTL I/O support. The ispMACH 5000VG family also supports GTL+, PCI, and PCI-X I/O configurations for use in high-speed bus interfaces.

sysCLOCK PLLs for Timing Control
The ispMACH 5000VG devices have two sysCLOCK PLLs that provide precise timing control for today's high-speed designs. Designers can generate complex clock waveforms with the clock multiply and divide capability of the PLL as well as adjust setup, hold and clock to output timings by shifting the clock under sysCLOCK control.

SuperWIDE Logic Blocks for High Performance
This family uses the proven SuperWIDE 68-input logic block that is found in other ispLSI 5000V devices, providing excellent support for emerging 64-bit applications. This SuperWIDE capability can lead to a 60% performance gain compared to devices with the more traditional 36-input logic block for complex logic functions. Additionally, Lattice has enhanced the ispMACH 5000VG logic block by increasing the maximum number of product terms per function from the 35 implemented in the ispLSI 5000VE series to 160. This leads to further performance improvements, up to 25% faster than architectures that support a maximum of 35 product terms per function.

Design Tools
The ispMACH 5000VG family is supported by Lattice's new ispLEVER™ Version 1.0 design tools available today from Lattice. The ispLEVER tools, Lattice's platform for next-generation logic design, provide designers with rapid access to the performance and features of the ispMACH 5000VG devices while maximizing resource utilization. This is achieved through timing driven placement & routing coupled with optimized synthesis support from vendors such as Exemplar and Synplicity. Lattice customers with valid software maintenance agreements will be upgraded to the new software suite during the first quarter of 2002.

Price and Availability
The ispMACH 5768VG is available now in 256- and 484-ball fine pitch Ball Grid Array (BGA) packaging featuring a space-saving 1 millimeter ball pitch. Projected pricing for the ispMACH 5768VG is as low as $33.00 in high-volume for the second half of 2002.

About Lattice Semiconductor Oregon-based Lattice Semiconductor Corporation designs, develops and markets the broadest range of high-performance ISP programmable logic devices (PLDs) and offers total solutions for today's advanced logic designs.

Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communications, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124 USA; Telephone 503-268-8000, FAX 503-268-8037. For more information on Lattice Semiconductor Corporation, access our World Wide Web site at http://www.latticesemi.com.

Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our silicon wafer suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements.

Lattice Semiconductor Corporation, L (& design), Lattice (& design), in-system programmable, ispLEVER, SuperBIG, SuperWIDE, ispMACH, ispLSI, sysCLOCK, sysIO, E2CMOS, ISP and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.

GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.

For more information contact:

Sean Hildenbrand, Public Relations
Lattice Semiconductor Corporation
sean.hildenbrand@latticesemi.com
(503) 268-8680