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Lattice Delivers 2nd Generation SuperWIDE™ 3.3V In-System Programmable High-Density PLDs-New ispLSI� 5000VE Family Expands Lattice 3.3V ISPTMPLD Leadership- HILLSBORO, Ore. - JANUARY 17, 2001 - Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the production release of its second-generation SuperWIDE In-System Programmable (ISPTM) Complex Programmable Logic Device (CPLD) Family, the ispLSI 5000VE family. Comprised of four devices, the family members offer from 128-macrocells to 512-macrocells featuring Lattice's high performance SuperWIDE logic blocks. The fastest member, the ispLSI 5128VE, debuts with a blazing 180MHz, 5ns pin-to-pin logic delay (Tpd). Through a combination of advanced sub-micron E2CMOS� silicon technology, an optimized architecture and enhanced circuit design, this 3.3 Volt second-generation BFW (Big-Fast-Wide) family of devices provides greater than a 30% boost in system performance over the previous ispLSI 5000V generation. "Lattice is setting the industry pace for new 3.3V ISP product introductions and is clearly the 3.3V CPLD market leader," stated Steve Stark, Lattice Director of Product Marketing. "With its proprietary 68 input, 32 macrocell SuperWIDE logic block, Lattice's ispLSI 5000VE devices feature the most advanced CPLD architecture available. This latest generation of devices will continue to reinforce our market supremacy." The ispLSI 5000VE family supports designs from 6,000 to 24,000 logic gates that require up to 256 I/O pins. The family features four members, the ispLSI 5128VE, ispLSI 5256VE, ispLSI 5384VE, and ispLSI 5512VE, that support today's mainstream CPLD density requirements. These 3.3-volt logic core devices also feature output pins that can be individually programmed to support 3.3- or 2.5-volt output levels. Boundary scan testing and ispJTAGTM in-system programming are executed via the on-board JTAG (IEEE 1149.1) test access port. The 68 input, 32 macrocell logic blocks of the new ispLSI 5000VE family deliver more than twice the logic capability of competitive CPLDs. The second-generation SuperWIDE architecture was further optimized, resulting in an additional increase in logic efficiency. The ispLSI 5000VE devices, like their predecessors, support concurrent combinatorial and registered function outputs from each macrocell to provide maximum logic utilization. They also feature multiple control options including programmable register Set, Reset and Clock Enable. Members of the ispLSI 5000VE family are available in a variety of advanced package options. 1.0 millimeter fine-pitch Ball Grid Array (fpBGA) packages are offered for higher I/O count members of the family, requiring less printed circuit board space than with standard BGA packages. The ispLSI 5000VE family of devices is supported in Version 8.2 of Lattice's ispDesignEXPERTTMlogic fitter, which supports logic design implementation with all leading CAE design tools. Price and AvailabilityThe ispLSI 5000VE devices are priced in fine-pitch BGA packages in high volume as follows: ispLSI 5128VE -- $9.00, ispLSI 5256VE -- $15.00, ispLSI 5384VE -- $25.00, and ispLSI 5512VE -- $40.00. All devices are available now. About Lattice SemiconductorOregon-based Lattice Semiconductor Corporation designs, develops and markets the broadest range of high-performance ISPTM programmable logic devices (PLDs) and offers total solutions for today's advanced logic designs Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communications, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124 USA; Telephone 503-268-8000, FAX 503-268-8037. For more information on Lattice Semiconductor Corporation, access our World Wide Web site at http://www.latticesemi.com. Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our silicon wafer suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements. # # #
Lattice Semiconductor, L (& design), Lattice (& design), in-system programmable, ispDesignEXPERT, SuperWIDE, ispLSI, E2CMOS, ispJTAG, ISP and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries. GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders. For more information contact: Steve Stark, Director, Product Marketing |
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