 |
||
 New Account
Sign In
|
Lattice Semiconductor Boosts SuperBIG 3.3V ISP PLDs to 1080 Macrocells
HILLSBORO, OR - MARCH 13, 2000-Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the new ispLSI 8000V family, the 3.3-Volt SuperBIG line of in-system programmable (ISP) CPLDs. The new low-voltage devices feature up to 1080 macrocells and up to 360 input/output registers for a total of 1440 registers, making them the largest complex PLDs available. The ispLSI 8000V devices couple very high densities with blazing fast operating frequencies of up to 125MHz and 8.5ns pin-to-pin logic delays (Tpd). The ispLSI 8000V family is based on the company's proprietary E2CMOS� electrically erasable technology and the advanced architecture of the popular ispLSI 8000 family. With this release, all of Lattice's innovative SuperBIGTM, SuperFASTTM and SuperWIDETM high performance PLDs are available in true 3.3V families, allowing designers to leverage the combined benefits of speed, 68-input wide logic, and high CPLD densities for all their low-voltage requirements. "Lattice continues to push CPLD densities with the ispLSI 8000V family while providing a roadmap for lower-voltage system design," said Stan Kopec, Vice President of Corporate Marketing for Lattice Semiconductor. "Even with their impressive densities, the SuperBIG devices provide superior system performance, enabling them to continue to encroach on traditional FPGA applications." The new SuperBIG ispLSI 8000V devices deliver high performance with pin-to-pin logic delays (Tpd) to 8.5 ns and an internal operating frequency (Fmax) of 125 MHz. The largest 3.3V device, the ispLSI 81080V contains 360 I/Os. All ispLSI 8000V device I/Os are 5-Volt tolerant and support user selectable 3.3V or 2.5V I/O. Boundary scan test and ispJTAGTM in-system programming are supported via the JTAG (IEEE 1149.1) test access port. Architecture The new ispLSI 8000V architecture features general-purpose macrocells contained in five, seven or nine Big Fast Megablocks (BFMs), respectively. Each BFM consists of six, 20-macrocell wide Generic Logic Blocks (GLBs) with 44 inputs per GLB. The popular architecture delivers both high-speed Global and Big Fast Megablock interconnects using a unique Global Routing Plane (GRP) architecture. Acting like a programmable silicon backplane, the GRP delivers high-speed 2-ns global interconnect. A second-generation product term sharing array supports up to 28 product terms per macrocell output. The ispLSI 8000V and 8000 SuperBIG devices are the industry's only PLDs to include an embedded tristate bus that can be configured as either twelve 9-bit buses or in combinations up to one 108-bit bus. Built-in bus arbitration logic prevents bus contention to improve performance and eliminate potential logic hazards. The embedded bus can be utilized as an internal bus or an extension of an external tristate bus and is excellent for microprocessor peripheral applications. Applications Lattice's SuperBIG ispLSI 8000V devices, with their wide input logic architecture and internal tri-state buses, are particularly well suited for high speed data processing and communications applications requiring interface with multiple system buses. Fast Programming Times Lattice delivers the fastest programming times in the industry with all its ISP devices featuring on-board programming times of less than five seconds. These fast programming speeds are the result of Lattice's advanced architectures and manufacturing processes. They are supported by the ispVMTM System, Lattice's "virtual machine" for programming devices from multiple vendors. Software Support The new ispLSI 8000V family of devices is supported by version 8.0 of Lattice's ispDesignEXPERTTM Systems for in-system programmable logic design, including the ispDesignEXPERT Compiler with Viewlogic and the ispDesignEXPERT System with Synplicity. These tools assist system designers in realizing the best implementations of increasingly more complex system-level functions. The third generation ispDesignEXPERT Logic Compiler is specifically designed to optimize VHDL- and Verilog-based logic designs synthesized by third-party HDL synthesis tools for the advanced architectures of Lattice's SuperBIG, SuperFAST and SuperWIDE ISP device families. Lattice's software tools support logic design implementation in all leading CAE environments. Pricing and Availability All family members are available today in the 272-BGA or 492-BGA packages. In a 272 BGA package, the ispLSI 8600V, ispLSI 8840V, and ispLSI 81080V are priced at $41.00, $52.00 and $65.00, respectively, in 1,000 piece quantities. About Lattice Semiconductor Oregon-based Lattice Semiconductor Corporation designs, develops and markets the broadest range of high-performance ISPTM programmable logic devices (PLDs) and offers total solutions for today's advanced logic designs. Lattice introduced in-system programmability to the logic industry in 1992. In June 1999, Lattice acquired Vantis, the corporation that invented the PAL� device and PLD switch matrix architecture, from AMD. With nearly double the R&D and sales resources, the resulting integrated company will focus on delivering logic products that satisfy the performance, density and ease-of-use requirements of its customers. Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communications, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124 USA; Telephone 503-268-8000, FAX 503-268-8037. For more information on Lattice Semiconductor Corporation, access our World Wide Web sites at http://www.latticesemi.com. Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties, including the effect of changing economic conditions, the effect of overall semiconductor market conditions, product demand risks, risks associated with dependencies on silicon wafer suppliers and semiconductor assemblers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements. # # # Lattice Semiconductor, L (stylized) Lattice, ISP, ispJTAG, ispLSI, ispVM, SuperBIG, SuperFAST, SuperWIDE, ispLSI 8000, and ispDesignEXPERT are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. For more information contact: Evelyn Leos, PR Manager |