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Lattice Delivers Industry's First, Complete Family of 2.5-Volt, High Density ISP PLD Devices
HILLSBORO, OR - OCTOBER 18, 1999 - Lattice Semiconductor (NASDAQ: LSCC) today announced the ispLSI� 2000VL, the first 2.5-Volt family of CPLDs fully available in the marketplace. The new device family provides the broadest range of advanced ISPTM low voltage logic devices ranging from 32 to 192 macrocells. Based on the advanced architecture of Lattice's SuperFASTTM CPLDs, the new family delivers 5- to 6- ns pin-to-pin logic delays and operating frequencies from 180- to 150-MHz, with a power savings of at least 50 percent. "While other companies have only announced their future 2.5-Volt offerings or are sampling just one device, Lattice is delivering an entire family of 2.5-Volt solutions today," states Steve Stark, Director of Marketing at Lattice Semiconductor. "By actually shipping a full line-up of five 2.5-Volt High Density PLDs now, Lattice is making next-generation 2.5-Volt programmable logic a reality, not just a promise." Device Family The ispLSI 2000VL family includes five device densities at 32, 64, 96, 128 and 192 macrocells, with general-purpose I/O counts from 32 to 128 pins. The ispLSI 2192VL and ispLSI 2128VL devices feature 6 ns Tpd (pin-to-pin logic delay) and 150MHz Fmax (clock frequency) performance, the ispLSI 2064VL and ispLSI 2096VL devices feature 5.5 ns/165 MHz (Tpd/Fmax) performance, and the ispLSI 2032VL device features 5.0 ns/180 MHz (Tpd/Fmax) performance. While operating with a 2.5-Volt logic core voltage and providing 2.5-Volt output levels, the ispLSI 2000VL family has input and I/O pins which are 3.3-Volt tolerant to assist system designs transitioning from 3.3-Volt to 2.5-Volt operation. The high performance and low power of the ispLSI 2000VL family makes these devices an ideal match for emerging 2.5V system applications, particularly those in the communications arena such as G3 wireless base stations, terabit routers, SONET optical data transmission networks and remote access servers. Packaging Devices are available in packages from 44 to 208 leads including PLCC, TQFP, PQFP and BGA configurations. The new BGA packages include Fine Pitch and Chip Array options, providing board space reductions of up to 70 percent compared with standard BGA technologies. Full JTAG-compliant in-system programming and boundary scan test is an excellent complement to Lattice's new, tighter pitch BGA packaging. These new, low voltage devices are pin-for-pin, drop in replacements for existing 3.3-Volt ispLSI 2000V and 2000VE devices. Like other Lattice devices, they feature a robust list of features including programmable pull-up resistors and slew rate control, hot socketing capability, programmable open-drain outputs and the industry's fastest programming times. Lattice's advanced proprietary E2CMOS� non-volatile process technology -- UltraMOS� -- has made it possible for Lattice to deliver both the world's highest density and fastest production PLDs while offering the industry's fastest in-system programming times -- critical advantages for ISP devices. Software Support The new ispLSI 2000VL family of devices is supported by a broad library of design tools including Lattice's recently released ispEXPERTTM systems. These systems are available for PC and workstation platforms, supporting logic design implementation in all leading electronic design environments. The third-generation logic compiler in Lattice's ispEXPERT systems is specifically designed to optimize VHDL- and Verilog-based logic designs synthesized by third-party HDL synthesis tools. All the advanced architectures of Lattice's recently announced ISP device families are supported. Pricing and Availability The complete ispLSI 2000VL device family, which includes the ispLSI 2032VL, 2064VL, 2096VL, 2128VL and 2192VL, is available today. Prices in high volume, depending on device density, package and speed grade, range from $2.00 to $19.00. About Lattice Semiconductor and Vantis Oregon-based Lattice Semiconductor Corporation designs, develops and markets the broadest range of high-performance ISP programmable logic devices (PLDs) and offers total solutions for today's advanced logic designs. Lattice introduced in-system programmability to the logic industry in 1992. In June 1999, Lattice acquired Vantis, the corporation that invented the PAL� device and PLD switch matrix architecture, from AMD. With nearly double the R&D and sales resources, the resulting integrated company will focus on delivering logic products that satisfy the performance, density and ease-of-use requirements of its customers. Lattice/Vantis products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communications, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124 USA; Telephone 503-268-8000; FAX 503-268-8037. For more information on Lattice Semiconductor or Vantis Corporation, access our World Wide Web site at http://www.latticesemi.com. Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties, including the effect of changing economic conditions, the effect of overall semiconductor market conditions, product demand and market acceptance risks, risks associated with dependencies on silicon wafer suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements. # # # Lattice Semiconductor, L (stylized) Lattice, ispLSI, ISP, in-system programmable, SuperFAST, SuperWIDE, UltraMOS, E2CMOS ispDOWNLOAD, ispEXPERT and ispJTAG are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other marks are the property of their respective holders. For more information contact: Evelyn Leos, PR Manager |