September 2011Extremely Small Footprint and Over 100X Power Reduction Highlight Benefits for Low Density PLD Designers
Samples of MachXO2 devices using a 2.5 x 2.5mm 25-ball Wafer Level Chip Scale Package (WLCSP) are now shipping. The MachXO2 devices combine an extremely small footprint - until now unprecedented in the PLD market - with the industry's lowest power and most feature-rich low density PLDs. Built on a low power 65nm process featuring embedded Flash technology, the MachXO2 family delivers a 3X increase in logic density, a 10X increase in embedded memory and more than a 100X reduction in static power compared to previous generations. With the industry's most robust PLD functionality, ultra-low power and new WLCSP packaging, the MachXO2 devices can now address applications previously not accessible to PLDs.
The MachXO2 family leads the industry in providing the lowest power and highest functionality of any PLD family. Now Lattice is extending its lead in the low density PLD market by offering a portfolio of small footprint die/package combinations for the MachXO2 family to be made available throughout 2011, including:
MachXO2 LCMXO2-1200ZE devices in the 25 WLCSP are now available as engineering samples, with production devices scheduled to be available by the fourth quarter of 2011. All other ultra-low footprint packages mentioned will be sampling by the end of 2011.
For more information about the MachXO2 PLD family and WLCSP packaging, visit the Lattice website.
© Lattice Semiconductor Corporation 2012
