September 2009The LatticeECP3 FPGA family provides the industry’s lowest-cost, lowest-power SERDES-capable FPGA with support for the SONET/SDH protocol, making it the best and highest-value programmable solution for wireline applications.
The LatticeECP3 FPGA family combines a high-performance FPGA fabric, high-performance I/Os and up to 16 channels of embedded SERDES with associated Physical Coding Sublayer (PCS) logic. Each channel of PCS logic contains dedicated transmit and receive circuitry for high-speed, full-duplex serial data transfer of up to 3.2 Gbps. The PCS logic in each channel can be configured to support an array of popular data protocols. In addition, the protocol-based logic can be fully or partially bypassed in a number of configurations to allow users flexibility in designing their own high-speed data interface.
The LatticeECP3 platform for SONET/SDH is ideal for backplanes and chip-to-chip interfaces and SONET framers. Some examples of applications that can benefit from this capability are shown below.
Examples of the LatticeECP3 FEC solution include:
LatticeECP3 SERDES also supports a variety of commonly-used protocols like SGMII and Gigabit Ethernet PCS, PCI Express, Serial RapidIO, CPRI, OBSAI, XAUI, SD/HD/3G-SDI and more.
To learn more about the LatticeECP3 FPGA family, visit the Lattice website or contact your local Lattice sales representative.
© Lattice Semiconductor Corporation 2012
