September 2009

LatticeECP3 FPGA Extends Low Power, Low Cost Benefits to More Complex Wireless and Wireline Applications

On August 24, Lattice annouced availability of its highest-density LatticeECP3 device, the LatticeECP3-150. This low-power FPGA is ideal for high-volume, low-cost 3G basestation designs and other complex wireless and wireline applications.

Features

• 149 K LUT4s of logic capacity to implement complex designs
• Up to 16 SERDES channels with data rates from 230 Mbps to 3.2 Gbps
• 6.8 Mbits of embedded memory and 303 Kbits of distributed RAM
• Fully-cascadable DSP architecture with 320 18x18 multipliers and powerful 54-bit ALU operation
• Two DLLs and ten PLLs
• Up to 586 I/O; programmable sysIO buffer support for a wide range of interfaces
• 1 Gbps LVDS I/O, with Input Delay blocks, allows interfacing to high-performance ADCs and DACs
• Low-cost wirebond packaging

Power

The LatticeECP3 family is built on an ultra low power, cost-optimized 65-nm process from Fujitsu. To further minimize power consumption the LatticeECP3 uses variable channel lengths, optimized low-power transistors, and improved routing defaults and algorithms. As a result, the LatticeECP3 family offers significantly lower Total Power than the competition.

For additional information on the methodology and measurements refer to the Power Considerations in FPGA Design (LatticeECP3) White Paper.

Intellectual Property

Lattice also provides Intellectual Property (IP) cores, development boards and software to enable designers to develop time-to-market solutions. A range of IP cores including CPRI, OBSAI, Serial RapidIO, XAUI, SGMII/Gigabit Ethernet, PCI Express, Tri-Rate SDI PHY for serial connectivity, FIR filters, FFT, Reed-Solomon Encoders, Reed-Solomon Decoders, CORDIC, CIC, NCO for DSP functions and several others for memory interfaces and connectivity are available. 

Software

The LatticeECP3 FPGA family is supported by the ispLEVER design tool suite, version 7.2 Service Pack 2 which provides a complete set of powerful tools for all design tasks, including project management, IP integration, design planning, power analysis, place and route, on-chip logic analysis and more. 

Applications

With its low power characteristics, small die size, low cost wirebond packaging, high performance DSP, I/O and multi-protocol SERDES, the LatticeECP3-150 is ideally suited for highly complex and integrated Wireless Remote Radio Heads (RRH) such as MIMO-based RF antenna solutions. 

The ECP3-150 FPGA also provides Wireline Access developers with unprecedented high-density, low-cost, low-power Ethernet, SONET and PCI Express solutions, with the lowest cost points and power footprints in the FPGA industry.

To Learn More

To learn more about the LatticeECP3 FPGA family, visit the Lattice website or contact your local Lattice sales representative.