September 2008

Improved SPI4.2 Interface Offers Numerous Benefits

Lattice's low-power, high-performance embedded SPI4.2 interface has been enhanced to include sophisticated link layer buffer management options.

Lattice offers the industry's lowest-power and highest-performance SPI4.2 interface as an embedded ASIC core in the LatticeSCM family. The LatticeSCM FPGA platform provides designers with multiple license-free, hardened SPI4.2 IP cores using Lattice's exclusive Masked Array for Cost Optimization (MACO) structured ASIC technology. These cores deliver pre-engineered, standard-compliant IP functions developed by Lattice to shorten end-system time to market, exponentially lowering device cost, power and PCB footprint targets. Recent improvements to the SPI4.2 interface provide designers with a programmable buffer manager that offers the following:

• Shared or per-channel buffer manager
• Up to 16 separate physical FIFOs per Tx/Rx direction
• Transmit Bandwidth Manager and Receive Channel Mapper
• Parameterizable packet overflow and packet error drop
• Graceful packet overflow drop
• Both store & forward as well as cut-through operation
• Parameterizable independent buffer depth per transmit and receive direction
• Per channel empty, almost empty, full and almost full status
• Programmable almost empty and almost full thresholds per channel
• Dynamic channel provisioning
• Programmable sequencer based scheduler

To Learn More

Further information on the SPI4.2 IP Core as well as a XAUI to SPI4.2 Bridge Solution can be found on the Lattice website.