September 2008

PAC-Designer Mixed Signal Design Tool Now Supports Automotive Versions of Power Manager II Devices

All Power Manager and ispClock devices also supported.

Lattice has announced the release of its PAC-Designer software design tool suite, version 4.99a. The tool suite now supports Lattice’s AECQ100-qualified automotive Power Manager II (LA-ispPAC-POWR1014/A) devices. The PAC-Designer tool suite also provides easy-to-use, point-and-click, intuitive design and verification support for all Power Manager and ispClock mixed signal devices.

Today’s automotive designs use advanced CPUs, FPGAs and ASICs, which increases the number of board-mounted power supplies. Using Lattice’s PAC-Designer software tools, designers can quickly implement and fine tune the power management algorithm used to control and monitor these diverse power supplies. The resulting board-specific power management design is more accurate, requires less circuit board area and costs less than traditional designs using multiple off-the-shelf dedicated devices.

Benefits of PAC-Designer Software

Common power management functions found on circuit boards include hot-swap control, voltage supervision, supply sequencing and reset generation. To ensure board reliability, all board-mounted power supplies should be sequenced and monitored via a power management algorithm. Typically, the power management algorithm is either changed or fine tuned during the board debug process to meet unforeseen device power-up behavior. Traditional solutions are hard-wired and cannot be changed without an expensive board re-spin. Lattice’s Windows-based PAC-Designer software enables implementation of a new power management algorithm in Lattice’s Power Manager II devices within minutes.

Similarly, clock network designs require timing adjustments during the board debug phase. The Lattice ispClock devices support an in-system programmable skew mechanism. Using PAC-Designer software, designers can precisely alter the clock skew of each of the clock nets. Traditionally, clock skew has been implemented by “snaking” clock traces on the board, and any change to the skew was implemented through a time consuming, expensive board re-spin. Using the PAC-Designer software, the clock network skew is altered simply by reprogramming the ispClock device.

About Lattice Automotive Power Manager II Devices

The Lattice Automotive Power Manager II device family includes the LA-ispPAC-POWR1014 and LA-ispPAC-POWR1014A. The LA-ispPAC-POWR1014 device integrates a 24-macrocell PLD and 10 analog voltage monitoring inputs, each with dual precision voltage monitoring comparators with an accuracy of 0.3%. In addition, the LA-ispPAC-POWR1014A device integrates a 10-bit Analog-to-Digital Converter (ADC) for voltage measurements and an I²C interface that enables a microcontroller or processor to read the status of all the comparators, inputs as well as outputs.  Both the POWR1014 and POWR1014A devices have been ruggedized to operate across a wide range of power supply voltages, from 2.8V to 3.9V. 

About Lattice ispClock Devices

There are two programmable Lattice ispClock families:

• ispClock5600A Family - In-system programmable zero-delay clock generation and distribution
• ispClock5300S Family - In-system programmable zero-delay clock distribution 

Users can standardize on these devices across a wide variety of designs instead of using a separate set of single-function clock devices on each board design.

The ispClock5600A devices provide seven on-chip counters for the generation of up to five clock frequencies. The E²CMOS-based ispClock5600A devices can source up to 20 clock outputs, each with independently programmable output skew, I/O standard and frequency selection.  

The ispClock5300S devices integrate a zero-delay buffer and fan-out buffers with independently programmable skew, I/O standard and output termination impedance.

Availability

PAC-Designer software is available now and can be downloaded free of charge from the Lattice website.