September 2008

This webcast provides an introduction to how power estimation is accomplished by FPGA design tools and which device features consume power and when. This information is applicable no matter which FPGA device you use, however Lattice FPGAs and design tools will be used to illustrate power calculation scenarios. This demonstration may encourage you to adopt a power verification strategy along with traditional simulation and static timing analysis.

Some designers skip timing simulation, not realizing that it can complement static timing analysis (STA) tools and help achieve timing closure faster. Don’t make the same mistake, identify and address problems earlier using a simulator and STA tools in concert. This Webinar will use a Lattice reference design throughout, to show you how to use STA results to prepare a test bench, extract timing models from FPGA design tools, understand simulation results, and identify/trace problems before you program your Lattice FPGA. To wrap-up the verification process, designers can compare timing results against functional results to ensure design integrity.

Lattice PCI Express IP Cores, Evaluation Boards and Demos

8/13/08

This webcast presents Lattice's PCI Express IP offerings, various hardware evaluation platforms, and the associated demos and reference designs for evaluating PCI Express. With PCI Express IP and the Lattice SG-DMA IP Core, Lattice offers a complete portfolio of demos that help designers evaluate the throughput through the PCI Express link and demonstrate a complete PCI Express system solution. These solutions offer designers an excellent starting point for their own PCI Express designs and allow them to make system-level architectural decisions even before they start their own designs.

Going forward, the movement is on from 3G to 4G. New, competing approaches such as WiMAX and LTE have arrived and base station topologies are evolving as well. Traditional implementations that co-locate the base station with the power amplifier and antenna are being replaced by distributed topologies where there is a central base station serving multiple remote antennas called Remote Radio Heads (RRH). This supports a smaller overall footprint and an overall lower cost for providers that facilitates the more rapid development of cellular networks.

Lattice offers an array of solutions to address this ever-changing market, starting with the Lattice ECP2M family. This unique family of devices offers designers the best of both worlds...a low cost FPGA fabric combined with the performance of integrated SERDES and DSP technology. This family serves as the ideal platform for various solutions including CPRI and OBSAI, high speed data conversion as well as RF and Baseband processing.