September 2007

Lattice Listens

Question:

What is the best way to connect my high-speed ADC devices to Lattice FPGAs?    

Answer:

There’s a class of high-speed Analog-to-Digital Converter (ADC) that supports sample rates ranging from 100Msps to 3Gsps. The common interface for most of these high-speed ADCs is LVDS Source Synchronous. The ADC supplies the digital data and associated clock via a single (or multiple) LVDS channels. The current generation of Lattice FPGA devices (LatticeSC/M, LatticeECP2/M and LatticeXP2) are ideally suited to capture digital data for further processing. These FPGA families offer:

• Pre-engineered high-speed I/O interface with double data rate capability to capture data.
• 1:4 I/O data rate gearing to step down the high-speed data rate to a lower clock rate for the FPGA fabric. 
• On-chip PLL and DLL to phase-adjust the incoming clock to properly capture the data.
• sysDSP blocks to further process the digital data efficiently through the FPGA.
• Once inside the FPGA fabric, you can route the digital data stream to the appropriate processor interface, to the high-speed SERDES interface or through many system-level IP functions, such as Ethernet or the LatticeMico32 soft processor core, to the external interface.

The LatticeECP2/M and LatticeXP2 FPGA families support serial LVDS links to the ADC device at data rates of up to 750Mbps. The LatticeSC/M FPGA family can support up to 2Gbps data rates.