September 2007One-hour webcasts available on the Lattice website.
Upcoming and recent Lattice webcasts are available live and on demand from the Lattice website and are shown in the table below. These one-hour webcasts are presented by Lattice technical staff and may include software demonstrations and question and answer sessions. To view any of the webcasts, go to the webcasts section of the Lattice website and select your topics of interest.
| Seminar Title | Featured Product | Date | Abstract |
|---|---|---|---|
| Implementing High-Performance PCI Express Solutions with Lattice and PLD Applications |
PLDA XpressLite PCIe Controller IP |
09/19/07 |
The LatticeECP2M device family offers pre-engineered and optimized support for PCI Express its innovative PCS (Physical Coding Sublayer) and embedded SERDES blocks, enabling the ability to rapidly develop and deploy FPGA-based system solutions. Lattice and PLD Applications (PLDA) have teamed together to offer a solution that combines PLDA's market-leading XpressLite PCI Express solution with LatticeECP2M device innovation. |
| Tips to Avoid Simultaneous Switching Output (SSO) Noise Problems |
ispLEVER Design Tool |
08/29/07 | The variety of I/O signal standards supported by FPGA devices can lead to hundreds of pins switching simultaneously. For reliable signal integrity, designers must account for potential noise effects and employ good design practices. This webcast addresses the symptoms of SSO-related problems, analysis tools, and design techniques to avoid noise problems. |
| Introduction to PAC-Designer and Power Manager II | ispPAC-POWR1014A and the PAC-Designer Design Tool |
08/22/07 |
This webcast provides a guided tour of how the PAC-Designer software tool is used to configure the ispPAC-POWR1014A, a mid-sized member of the Power Manager II family. |
| IP Cores for DSP and FPGA Designs | DSP IP Cores and LatticeXP2 and LatticeECP2/M FPGA Families |
08/14/07 | This webcast provides a broad spectrum of IP core options, what to look for in choosing a core, and some of the development issues involved in using vendor-supplied or third-party IP cores. This one hour panel discussion covers the keys to selecting an FPGA-based IP solution for DSP and other DSP IP topics. |
| Implementing Video & Graphics Intellectual Property in FPGAs | EasyLCD IP Core and FPGA Module |
08/08/07 | IP solutions for graphics and video display controllers used in embedded applications. Topics discussed include embedded system designer architecture considerations, how FPGAs can be used to integrate multiple graphic system functions and a review the implementation of the EasyLCD graphics and video processing IP and system. |
| SERDES Fundamentals |
LatticeSC/M and LatticeECP2/M FPGA Families |
07/31/07 |
View this webcast and learn the fundamentals of a SERDES-based interface, including the basics of Source Synchronous and CDR (Clock Data Recovery), when and how to use Source Synchronous vs. CDR, what makes Source Synchronous and CDR work and pointers on how to bring up the CDR hardware interface. |
© Lattice Semiconductor Corporation 2012
