October 2010Increasing demand for video, voice and data services has resulted in carriers having to deploy more Internet Protocol (IP) based systems using Ethernet technology. A typical Ethernet-based system architecture consists of an Ethernet switch connected to a series of line cards with 10 Gbps links (XAUI). Designers face the challenge of developing a programmable bridge between the various components such as framers, network processors on the line card and the Ethernet switch.
Typical Line Card
SPI4.2 is a popular high-speed parallel interface that can run in excess of 10 Gbps for network processors, traffic managers, media access controllers (MACs) and more. SPI4.2 utilizes a parallel 16-bit wide LVDS transmit and receive source synchronous interface. The SPI4.2 specification supports up to 256 channels per link.
There are significant physical and protocol differences between SPI4.2 and XAUI. Because of this, a SPI4.2 interface must be bridged to connect to a XAUI link. Until now, designers could implement full-rate SPI4.2 bridges supporting complex packet flow and traffic management policies mainly on premium FPGA devices. Designers can now use the LatticeECP3 FPGA and SPI4.2 and XAUI IP cores, along with their bridging logic, to develop a low-power, high-value SPI4.2 solution.
XAUI-to-SPI4.2 Bridging Application
The LatticeECP3 FPGA family is comprised of five devices that offer standards-compliant multi-protocol 3.2G SERDES, DDR/DDR2/DDR3 memory interfaces and high-performance, cascadable DSP slices that are ideal for high-performance RF, baseband and image signal processing. LatticeECP3 FPGAs also feature fast 1 Gbps LVDS I/O, as well as embedded memory of up to 6.8 Mbits. Logic density varies from 17K LUTs to 149K LUTs with up to 586 user I/O.
The SPI4.2 IP core requires about 4,000 look-up tables (LUTs) in 128-bit mode for a full 256-channel static mode core. It can be implemented along with other user logic in all LatticeECP3 family members, from the LatticeECP3-17 device through the largest member of the family, the LatticeECP3-150 device. The SPI4.2 core operates at interface speeds of up to 11.2 Gbps, while fulfilling all requirements of the SPI4.2 interface protocol, including support for up to 256 logic channels, calendars, transmit and receive status, programmable burst size and DIP4 error checking.
The XAUI IP core for LatticeECP3 FPGAs provides a solution for bridging between XAUI and 10-Gigabit Media Independent Interface (XGMII) devices. It implements 10Gb Ethernet Extended Sublayer (XGXS) capabilities in soft logic that together with PCS and SERDES functions implemented in the FGPA provides a complete XAUI-to-XGMII solution. Users can evaluate the XAUI functionality by downloading the LatticeECP3 XAUI Demo.
For further information about the various IP cores available visit the Lattice IP Cores and Reference Designs web page. A list of LatticeECP3 Evaluation Boards and Demos is also available.
© Lattice Semiconductor Corporation 2012
