October 2010

Implementing Low-Cost DDR3 Solutions with LatticeECP3

DDR3 SDRAM is the latest mainstream generation SDRAM memory technology that features faster speed and throughput, mitigated simultaneous switching output (SSO) noise, and reduced routing due to "fly-by" routing signals to SDRAM, instead of a low-skew tree distribution.

The pre-engineered source synchronous logic implemented in the LatticeECP3 FPGA I/O supports various high-speed interfaces including 800Mbps DDR3 memory technology with read and write leveling.

DDR3 SDRAM Controller IP Core

The DDR3 SDRAM Controller IP core connects to the LatticeECP3 DDR3 memory interface blocks (I/O modules) and clocking circuitry to provide users with an out-of-the-box solution for interfacing to DDR3 memory components and DIMMs. The controller implements a number of features to improve overall throughput, including:

• Command pipelines
• Efficient bank management techniques to manage multiple banks in parallel

DDR3 SDRAM Controller IP Core Block Diagram

LatticeECP3 DDR3 Demo Design

The LatticeECP3 DDR3 Demo Design is available for download from the Lattice web site. Designers can use the design to see the functionality of the DDR3 SDRAM Controller IP core running at a speed of 400 MHz (800 Mbps) on the LatticeECP3 I/O Protocol Board which has two sockets that can accommodate two DDR3 memory modules.

The LatticeECP3 DDR3 Demo Design consists of two major parts:

• DDR3 SDRAM Controller IP core: The demo supports the parameterized DDR3 data bus widths (8-, 16-, 32-, and 64-bit configurations). The user logic is also parameterized by the core parameter file. A DDR3 SDRAM Controller IP core configuration file for the 64-bit data width is provided in the demo package.
• User Logic Block provides the following functions: State machine programs the mode registers and controls DDR3 read and write operations, address generation, write data generation, read data validation, and control and observation.

LatticeECP3 DDR3 Demo Design Block Diagram

To Learn More

For further information about LatticeECP3 FPGAs, download the LatticeECP3 Data Sheet. For details on LatticeECP3 high-speed I/O interfaces, see technical note TN1180, LatticeECP3 High-Speed I/O Interface.