October 2009

Lattice Delivers High-Speed Broadcast Video Connectivity Solution

Lattice's complete platform for SMPTE applications provides a cost-effective and flexible approach to the challenges of multi-rate broadcast for SD, HD and 3G SDI.

In broadcast studio equipment, there is no prior knowledge of what the Rx data rate will be. As a result, designers for this equipment would like to see dynamic “on-the-fly” support for various popular data rates such as:

• SD-SDI (SMPTE 259M) at 270 Mbps
• HD-SDI (SMPTE 292M) at 1.485 Gbps
• 3G-SDI (SMPTE 424M) at 2.97 Gbps

Preferably, each of these rates should be supported on every pin of the component that receives and processes these physical links.

Lattice offers designers a complete platform for SMPTE applications, including: 

• The mid-range, high-value LatticeECP3 FPGA
• The LatticeECP3 Video Protocol Board
• The Tri-Rate SDI PHY IP Core and demos

Enhanced SMPTE Support in LatticeECP3 FPGAs

LatticeECP3 devices simultaneously and dynamically support the rates listed above without oversampling. The ECP3 SERDES is fully compliant to the SMPTE jitter specifications. The SERDES I/Os can also be DC-coupled (with external capacitors) to support SMPTE pathological signals. Additionally, the ECP3 SERDES has been architected for channel independence. The device includes the appropriate clock dividers to allow designers to implement truly Independent Transmit Multi-Rate Support for SD/HD/3G. The receive clocking is independent per channel and can be sourced externally or from the FPGA, allowing independent multi-rate receive support for SD/HD/3G.

Lowest Component SMPTE Solution

There are numerous clocking solutions possible, depending on whether the requirements are single rate (like HD only), tri-rate with integer frame rates or the more complex tri-rate with mixed integer and fractional frame rates. VCXOs, fixed frequency oscillators, or crystals could all be used. All of these combinations tend to increase the number of clocks and external components on the PCB.

The figure below shows a block-level representation of components required for a Tri-Rate Integer/Fractional implementation using the LatticeECP3. A 270 MHz clock input is required for supporting mixed SD - fractional frame rate HD/3G transmission in the same quad using LDR.  The IPexpress tool within the ispLEVER software suite generates the two required IP blocks, the SERDES PCS block and the Tri-Rate SDI PHY IP Core block.

Typical Multi-Rate Clocking Solution Using LatticeECP3 FPGAs

The LatticeECP3 SMPTE solution:

• Requires a low cost, relaxed specification 27 MHz oscillator for the entire clocking solution.  An additional 45Mhz 50ppm oscillator is required if fractional frame rate HD/3G and SD need to be transmitted from different channels of the same SERDES quad.
• Requires a clock cleaner (common in the industry) prior to driving the SERDES TX reference clock
• Uses cable drivers and equalizers to drive/terminate the 75ohm SMPTE connections
• Does not require high-power, expensive in-line reclockers to meet tight jitter specifications
• Does not require high-power clock generation ASSPs. All clock generation is done on-chip with available PLLs. Benefits are lower power, reduced board space and lower cost.

Lowest Power SERDES-Capable FPGA in the Industry

The LatticeECP3 family is built on an ultra low power, cost-optimized 65-nm process from Fujitsu. To further minimize power consumption the ECP3 uses variable channel lengths, optimized low-power transistors, and improved routing defaults and algorithms. As a result, the ECP3 family offers significantly lower Total Power than the competition.  
 

Total Power Comparison

For additional information on the methodology and measurements, refer to the Power Considerations in FPGA Design (LatticeECP3) White Paper.

LatticeECP3 Video Protocol Board

The LatticeECP3 Video Protocol Board features the LatticeECP3-95 in a 1156-ball fpBGA package. This stand-alone evaluation board provides a functional platform for development and rapid prototyping of many different video applications.

The LatticeECP3 FPGA family includes innovative features for broadcast video applications. SMPTE standards (SD-SDI, HD-SDI and 3G-SDI) and DVB-ASI can be implemented using on-board 75ohm BNC connectors. 7:1 LVDS video interfaces like ChannelLink and CameraLink can be supported by the generic DDRX2 mode on the I/O pins. Expansion ports are also available for other display interfaces such as HDMI.

LatticeECP3 Video Protocol Board

Tri-Rate SMPTE SDI Demo

The Tri-Rate SMPTE SDI Demo shows the capability of the LatticeECP3 SERDES with an SD/HD/3G design example. The design is implemented using the LatticeECP3 Video Protocol  Board. It includes a Pattern Generator, Pattern Checker and the Lattice Tri-Rate SDI PHY IP Core.

This design supports two operational modes, Pass-Through mode and Pattern-Generation mode. The mode switching and the controls of these two modes are done by the on-board switch and push-buttons.

When in Pass-Through mode, the serial video stream is received, descrambled and word-aligned by the IP core receiver. Then, the Contrast/Brightness/Hue/Saturation adjustment module can optionally process the received parallel video data. Finally, the parallel video data is sent to the IP core transmitter for data scrambling, line number insertion and CRC insertion before it is sent out.

When in Pattern-Generation mode, an internal pattern generator will generate patterns for the IP core transmitter to send out color bars or pathological signals. The receiver can also be enabled in this mode for comparing the received video data with an internal pattern checker. The comparison errors will be sent out through a UART/RS-232 port and captured into a PC text file. A typical application is to generate test patterns and loop them back externally through an SDI cable to the checker. The test patterns can be pathological test patterns for EQU/PLL tests or simply color bar patterns through a very long SDI cable

To Learn More

The LatticeECP3 FPGA offers the lowest-power, lowest-component, lowest-cost solution for SMPTE applications. For further information, visit the Lattice SMPTE solutions web page. Contact your local Lattice sales representative to receive a demonstration of the Lattice Tri-Rate SMPTE solution.