October 2009

Lattice and Epson Slash Costs for SERDES and Video Reference Clocks

ispClock5400D and SG-710ECK meet XAUI and SD-Video jitter specs.

Lattice Semiconductor and Epson Corporation are pleased to announce low-cost reference clock solutions for SERDES and video applications using the ultra low noise, programmable differential interface ispClock5400D and the low-cost CMOS oscillator SG-710ECK. This solution replaces more expensive traditional high-frequency, differential clock sources.

SERDES and video applications use expensive differential interface oscillators with frequencies greater than 150 MHz to meet stringent jitter specifications. The Lattice ispClock5400D, using its low phase noise on-chip PLL, generates a higher clock frequency using Epson’s low-cost, lower-frequency oscillators with CMOS interface. The programmable output interface of the ispClock5400D device can meet any of the popular differential interface requirements. With this reference clock, the LatticeECP3 FPGA implementing XAUI and SDI video functions meets jitter requirements across the industrial temperature range.

The ispClock5406D and ispClock5410D are in-system-programmable differential clock distribution ICs designed for use in high-performance communications and computing applications such as PCI Express, ATCA, MicroTCA, and AMC. The ispClock5400D family features the CleanClock ultra-low phase noise, third-generation PLL. The FlexiClock output section supports multiple logic standards and dual skew control features.

ispClock5400D Block Diagram

The configuration of each device is held in on-chip non-volatile memory that is reprogrammable through a JTAG interface. Certain aspects of the device can be modified on-the-fly via an I²C interface. The ispClock5400D architecture is built around a high-performance ultra-low jitter PLL with programmable input, feedback, and output interface standards. Each output’s time and phase skew can be individually and precisely controlled to compensate for differences in board trace lengths or timing requirements of the receiving devices. Additionally, each output can be individually configured for fan-out buffer (FOB) or zero-delay buffer (ZDB) operation.