October 2008

Accelerate Display Interface Design with 7:1 LVDS Reference Design

Learn how the high-performance I/O capabilities of LatticeECP2/M FPGAs can be used in display applications for the consumer, automotive and industrial instrumentation markets.

The majority of Flat Panel Displays (FPD) use a system architecture where video data is received by a video interfacing board and is then transmitted to a display board that handles final video processing and display driving functions. The interface between these boards normally uses a high-speed interface referred to as 7:1 LVDS (Low Voltage Differential Signaling). This interface has multiple high-speed data lines typically operating at 200 to 800 Mbps and a lower-speed clock. Seven data bits are sent during each cycle of the low-speed clock.

Typical Flat Panel Display Architecture

Traditionally, implementing 7:1 interfacing in low-cost FPGAs has been challenging for three reasons:

• Implementation of high speed LVDS buffers
• Generation of low-skew, high-speed clocks for data recovery
• Mismatch between interface speed and FPGA fabric speed

The low-cost LatticeECP2/M and non-volatile LatticeXP2 FPGAs contain a number of features that make the implementation of 7:1 interfaces possible:

• 840 Mbps LVDS buffers
• PLLs and low-skew edge clocks for clock generation
• Pre-engineered gearbox logic for matching I/O and fabric speeds

Lattice 7:1 LVDS Video Demo Kit

To allow designers to rapidly implement 7:1 LVDS interfaces within the LatticeECP2/M and LatticeXP2 devices, Lattice provides a reference design and demo kit. See the Lattice website for more further information.