October 2007

Lattice and Avnet Offer High Speed Interface SpeedWay Design Workshops

Learn how to implement PCI Express, DDR2 and SERDES interfaces with LatticeECP2M FPGAs.

Lattice and Avnet Electronics Marketing, a division of Avnet, Inc., have developed a new workshop series featuring high-speed interfaces for Lattice's latest series of FPGAs. Designers, developers and engineers interested in leveraging the latest high-speed interface technologies with FPGAs can get hands-on experience by attending the Avnet-Lattice High Speed Interface SpeedWay Design Workshops, scheduled to take place this fall in locations throughout the U.S. and in Canada.

Avnet's factory-trained field applications engineers (FAEs) have developed materials for the full-day SpeedWay Workshops with support from Lattice's applications engineers. Based on practical experience and the latest technologies that highlight proven design techniques, attendees will leave these workshops armed with design knowledge and information that can be applied immediately to current projects.

Upcoming Locations

• Oct. 23 -  Baltimore, MD
• Oct. 30 -  Irvine, CA
• Nov. 1 -  San Jose, CA

Workshop Agenda

• 8:00 - 8:30, Registration
• 8:30 - 9:15, SERDES 101
• 9:15 - 10:45, Labs 1 & 2: ispLEVER Introduction, IPexpress Introduction, SERDES IP, SERDES Demonstration
• 11:00 - 12:00, PCI Express Architecture
• 12:00 - 12:30, Lunch
• 12:30 - 1:00, PCI Express Design Considerations
• 1:00 - 2:00, Lab 3: PCI Express IP and PCI Express Demonstration
• 2:15 - 3:00, DDR2 Design Considerations
• 3:00 - 4:00, Lab 4: DDR2 IP and DDR2 Demonstration

Registration

Workshop attendees will also receive a LatticeECP2 Advanced Evaluation Board (a $2400 value) with their $149 paid registration. For more information, or to register for a workshop, visit the Avnet website.