November 2010

PCI Express Root Complex-Lite IP Core for Low Cost FPGAs

Lattice has announced the availability of a PCI Express Root Complex (RC) Lite IP core based on the LatticeECP3 and LatticeECP2M FPGA families for use in simple bridging applications to any legacy host bus.

In the PCI Express hierarchy an endpoint operates as an upstream device and cannot communicate downstream. A root complex device, on the other hand, can communicate downstream. However, a full-featured root complex implementation is quite expensive in terms of FPGA gates used. Instead, a “lightweight” root complex core with a sub-set of the transaction layer functionality is adequate for implementing most bridging functions.

As shown in the figure above, the bridge is comprised of two basic building blocks. The first block is the PCI Express root complex (or Root Complex-Lite) IP core, which interfaces with the PCI Express endpoint device. The second block is the bridge logic that interfaces to the local bus/parallel interface. Using a low-cost FPGA like the LatticeECP3 or LatticeECP2M, designers have the flexibility to customize the design based on specific interface needs while absorbing other functions to reduce cost.

IP Core

The PCI Express Root Complex-Lite IP Core provides a x1 or x4 root complex solution from the electrical SERDES interface, physical layer, data link layer and a minimum transaction layer in the PCI Express protocol stack. The IP core is supported by the IPexpress FPGA design tool module within the Lattice Diamond and ispLEVER software. The x1 RC-Lite IP core requires approximately 4,500 FPGA look-up tables in 16-bit mode. The x4 RC-Lite IP core requires approximately 10,500 FPGA look-up tables in 64-bit mode.

Demo Bitstream

To help demonstrate the IP core, a LatticeECP3 PCI Express Root Complex Lite x1 Native Demo is available for download. The demo uses two LatticeECP3 I/O Protocol Boards connected via SMA cables to illustrate a x1 PCI Express link between two ports. One board functions as the downstream port (Root Complex) while the other functions as the upstream port (endpoint).

Next Steps

Read the Implementing PCI Express Bridging Solutions in an FPGA White Paper to learn more. Contact your local Lattice sales office to request a demonstration .