November 2010

New PAC-Designer 6.0 Software Enables Designers to Transform Board Management with Platform Manager Devices

The new PAC-Designer design software version 6.0 is now available. This new version enables analog and board designers to integrate a circuit board's power management and digital board management functions into the newly-announced Platform Manager device.

With PAC-Designer 6.0, designers can use a simple, easy-to-learn, push-button design methodology to implement designs into the FPGA portion of the Platform Manager device. Three new reference designs and an IP core are also available.

Simultaneously, Lattice has announced the new ispLEVER 8.1 SP1 Starter software, which also supports the digital design portion of Platform Manager devices. This capability can be used for more complex digital designs targeted to the FPGA section of the Platform Manager device.

For ease-of-use, PAC-Designer 6.0 software is provided as the primary design entry tool for Platform Manager devices. For more detailed control over complex digital designs, ispLEVER Starter 8.1 SP1 software can be used. Complete instructions on downloading, installing and using the software to create a working Platform Manager design can be found on the Lattice web site.

IP Cores and Reference Designs

Lattice provides three reference designs and an IP core that speed implementation of functions commonly implemented in Platform Manager devices:

Reference Designs:

• Board Fault Monitoring and Logging
• Closed Loop Power Supply Trimming
• Long Delay Timer Functions

IP Core:

• Platform Management Utility Functions IP Core - includes serial system communications options (I²C or SPI), closed-loop power supply trim options and fault logging options)

Availability

PAC-Designer 6.0 and the companion ispLEVER 8.1 SP1 Starter for Windows are available now for free download from the Lattice web site.

About the New Lattice Platform Manager Family

The Platform Manager product family consists of two devices, the LPTM10-1247 and LPTM10-12107. The LPTM10-1247 device can monitor 12 voltage rails and supports 47 combined digital inputs and digital outputs, while the LPTM10-12107 monitors up to 12 voltage rails and supports 107 combined digital inputs and digital outputs. Functionally, these devices include both a power management section and a digital board management section. The power management section consists of a programmable threshold, precision differential input comparator block with an accuracy of 0.7%, a 48-macrocell CPLD, programmable hardware timers, a 10-bit analog to digital converter and a trim block for the trimming and margining of supplies. The digital board management section consists of a 640-LUT FPGA and programmable logic interface I/O.