November 2009

PAC-Designer 5.2 Supports New Power Manager II Devices and HDL Verification

Lattice released version 5.2 of the PAC-Designer mixed signal design tool suite this month with new device support and productivity features. The PAC-Designer 5.2 software now supports two new higher-performance Power Manager II products: the ispPAC-POWR1014-2 and ispPAC-POWR1014A-2 devices. The POWR1014/A-2 devices are ideal for integrating Hot Swap control, voltage rail supervision and power supply sequencing ICs. PAC-Designer 5.2 software also supports an expanded input operating frequency range of 40 to 400 MHz for ispClock5400D devices and a new graphical editor for phase and time skew programming.

Power Manager II devices are commonly used to integrate discrete ICs for power management such as voltage supervisors, reset generators, watchdog timers and Hot Swap controllers. As more digital management functions are integrated, the verification step in the design flow depends on robust simulation technology. By adding HDL export features to PAC-Designer software, power supply sequencing, reset signal distribution, and other digital logic integrated into a Power Manager II device can be simulated with IEEE industry standard Verilog HDL or VHDL. This allows for functional verification of sequence and supervisory logic by the Aldec Active-HDL Lattice Web Edition simulator.

Lattice's PAC-Designer software for Windows is available now at no charge for download from the Lattice website.