November 2008

ispLEVER SSO Analyzer - An Industry First!

As high-speed I/Os have become the norm with FPGA solutions, Simultaneous Switching Output (SSO) noise is more apparent and can lead to signal integrity problems at the PC board level. With the release of ispLEVER 7.1, Lattice has introduced the industry’s first SSO interactive analyzer to help designers make good I/O planning decisions and avoid SSO noise issues.

ispLEVER Design Planner

The SSO Analyzer determines the level of noise generated by output pins that switch at the same time. This is directly related to a design’s pin placement. Therefore, it makes sense to find the SSO Analyzer software within the Design Planner program (see design flow diagram below). The Design Planner allows FPGA designers to set many design attributes including:

• I/O package pin signal assignments
• I/O type (LVCMOS, LVTTL, LVDS, etc)
• Slew rate
• Drive strength
• I/O bank assignment

Lattice FPGA Design Flow with SSO Analyzer

Calculating Noise

Let’s start with a look at the theory behind SSO noise calculations. There are two types of analysis: bank-based and the more accurate pin-based. Bank-based analysis is performed when some of the I/Os have been placed in a particular group or “bank” but have not yet been locked to a pin. This is the default for pre Place and Route (PAR) analysis. In this situation, all pins will be placed adjacently in the bank, which will generate the worst possible SSO noise. Pin-based analysis is done when all the I/Os have been locked to pins, the default for post-PAR analysis.

Each I/O type has a particular SSO noise curve. The figure below shows such a curve where the Y-axis provides SSO noise measured in mV and the X-axis is the number of I/Os that are switching simultaneously. If we look at a particular simulation with four pins switching at the same time with no specified locations, bank-based analysis will be performed. As you can see in the chip diagram, to provide worst-case analysis, the pins are placed adjacent. To read the curve, we simply locate the X-axis value of “4” and find the corresponding Y value of 4mV of noise.

SSO Noise Estimation - Bank-Based

The figure below shows a similar SSO noise curve for pin-based analysis where two pins have been locked. To enable calculations, a “victim” pin is assigned as the reference to determine the pin that will receive the worst SSO noise. We read the SSO noise curve one pin at a time. So, for the pin locked five pins away from the victim the net noise is determined by subtracting the SSO noise value of I/O 5 on the curve and I/O 4, or in this case 4.5mV – 4.0mV which equals 0.5mV. Following the same approach for the second pin, 10.2mV - 9.9mV results in 0.3mV. Therefore, the total SSO noise experienced by the victim pin is 0.8mV. The victim is now changed and the calculation repeated to find the worst value of any available pin.

SSO Noise Estimation - Pin-Based

Design Planner Spreadsheet View

The SSO Analyzer in ispLEVER handles all these calculations automatically and provide an easy-to-use interface from within the familiar Design Planner. In order to perform SSO analysis, the software tool needs some added information from the designer. Five new fields in the Design Planner “Spreadsheet View” have been added to accomplish this, as shown in the figure below:

• Outload - The capacitive load that the outputs will drive, measured in pF
• Switching ID - A user-defined identifier that tells the software which signals switch together
• PCB SSO Noise - The value of noise measured on the board for a particular I/O in mV
• SSO Allowance - The safety margin from Vih to Vil desired, expressed as a percentage

Design Planner, Spreadsheet View

Design Planner Package View

The software will detect SSN conditions on banks or pins, provide detailed reports and color-coded display of potential problems in the Package View of the Design Planner. The figure below highlights these features. The SSO Noise Histogram shows the percentage of noise for each device I/O bank. There is also a green or red pin highlight on the package diagram corresponding to SSO pass or fail so it is easy to spot problem areas. The SSO details for each pin are available in a pop-up window when you roll over the pin with the cursor.

Design Planner, Package View

You can also view a comprehensive SSO Report by clicking on “I/O SSO Analysis Report” in the PAR section of the ispLEVER Process window. Pass/fail status is highlighted in green/red for easy referencing. The user settings are included in the report so it is easy to reproduce and keep track of all the design parameters contributing to the SSO results.

SSO Analyzer Report

If the Analyzer finds SSO issues, there are a number of steps you can take to correct the problem. One of the easiest things to try first is to reduce the I/O slew rate for your design. You may want to reduce the I/O loading, choose lower drive strengths or spread the I/O placement in the package.

SSO analysis during the course of I/O planning can help designers mitigate noise conditions early in the design flow, thus saving time and preventing reliability issues later on. The Lattice SSO Analyzer is a unique tool to assist designers in performing this vital analysis. And currently such a tool for FPGA design is only available from Lattice. 

To Learn More

For more information about the Lattice ispLEVER software tools including the new SSO Analyzer, visit the Lattice website, or contact your local Lattice sales representative.